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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD6623 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 4-channel, 104 msps digital t ransmit signal processor (tsp) functional block diagram sp ort ram coefficient filter data scaler and power ramp cic5 filter rcic2 filter nco i q chan a i q i q i q jtag cs a[2:0] mode rw dtack ds d[7:0] in qin sync oen qout out [17:0] sdina sdfia sdfoa sclka sdinb sdfib sdfob sclkb sdinc sdfic sdfoc sclkc sdind sdfid sclkd sdfod summation scaler and power ramp cic5 filter rcic2 filter nco i q chan b i q i q i q scaler and power ramp cic5 filter rcic2 filter nco i q chan c i q i q i q scaler and power ramp cic5 filter rcic2 filter nco i q chan d i q i q i q microport clk reset 4 [17?] sp ort ram coefficient filter data sp ort ram coefficient filter data sp ort ram coefficient filter data nco = numerically controlled oscillator/tuner tdl tms tck trst tdo features pin compatible to the ad6622 18-bit parallel digital if output real or interleaved complex 18-bit bidirectional parallel digital if input/output allows cascade of chips for additional channels clipped or wrapped over range two? complement or offset binary output four independent digital transmitters in single package ram coefficient filter (rcf) programmable if and modulation for each channel programmable interpolating ram coefficient filter /4-dqpsk differential phase encoder 3 /8-psk linear encoder 8-psk linear encoder programmable gmsk look-up table programmable qpsk look-up table all-pass phase equalizer programmable fine scaler programmable power ramp unit high speed cic interpolating filter digital resampling for noninteger interpolation rates nco frequency translation carrier output from dc to 52 mhz spurious performance better than ?00 dbc separate 3-wire serial data input for each channel bidirectional serial clocks and frames microprocessor control 2.5 v cmos core, 3.3 v outputs, 5 v inputs jtag boundary scan applications cellular/pcs base stations micro/pico cell base stations wireless local loop base stations multicarrier, multimode digital transmit gsm, edge, is136, phs, is95, tds cdma, umts, cdma2000 phased array beam forming antennas software defined radio tuning resolution better than 0.025 hz real or complex outputs
rev. a AD6623 ? table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 logic inputs (5 v tolerant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 logic outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 idd supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 5 microprocessor port timing characteristics . . . . . . . . . . . . 6 microprocessor port, mode inm (mode = 0) . . . . . . . . . . . . . 6 microprocessor port, motorola (mode = 1) . . . . . . . . . . . . 6 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 explanation of test levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin configuration ?128-lead mqfp . . . . . . . . . . . . . . . . . . . . . . . . 11 128-pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin configuration ?196-lead cspbga . . . . . . . . . . . . . . . . . . . . . . 13 196-pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 microport control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 jtag and bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 control register address notation . . . . . . . . . . . . . . . . . . . . 15 serial data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial master mode (scs = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial slave mode (scs = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial data framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 self-framing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 external framing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial port cascade configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 programmable ram coefficient filter (rcf) . . . . . . . . . . . . . 16 overview of the rcf blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 interpolating fir filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 channel a rcf control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 psk modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 /4-dqspk modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8-psk modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 /8-8-psk modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 msk look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 gmsk look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 qpsk look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 phase equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 fine scale and ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 fine scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 rcf power ramping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ramp triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 special handling for sync0 pin-sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 cascaded intergrator comb (cic) interpolating filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cic scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cic5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 the rcic2 resampling interpolation filter . . . . . . . . . . . . . . 25 permissible values of l rcic2 and m rcic2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 frequency response for rcic2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 programming guidelines for AD6623 cic filters . . . . . . . . . . . . . . . . . . . 26 numerically controlled oscillator/tuner (nco) . . . . . 27 phase dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 amplitude dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 phase offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 nco frequency update and phase offset update hold-off counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 nco control scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 summation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 dual 18-bit output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 output clip detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 cascading multiple AD6623s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 selection of real and complex data types . . . . . . . . . . . . . . . . . . . . . . . . 29 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 hold-off counters and shadow registers . . . . . . . . . . . . . . . . . . . . . . . . . 29 start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 start with no sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 start with softsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 start with pin sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 set frequency no hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 hop with softsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 hop with pin sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 beam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 set phase no beam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 beam with softsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 beam with pin sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 time slot (ramp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 set output power, no ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 time slot (ramp) with softsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 time slot with pin sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 multicarrier scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 single carrier scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 microport interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 microport control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 external memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 intel nonmultiplexed mode (inm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 motorola nonmultiplexed mode (mnm) . . . . . . . . . . . . . . . . . . . . . . . . . 35 external address 7 upper address register (uar) . . . . . . . . . . . . . . . . . . 35 external address 6 lower address register (lar) . . . . . . . . . . . . . . . . . . 35 external address 5 softsync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 external address 4 sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 external address 3:0 (data bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 internal control registers and on-chip ram . . . . . . . . . . . . . 36 AD6623 and ad6622 compatibility common function registers (not associated with a particular channel) . . . . . . 36 channel function registers (0x1xx = ch. a, 0x2xx = ch. b, 0x3xx = ch. c, 0x4xx = ch. d) . . . . . . . . . . . . . . . . . . . . 36 (0x000) summation mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x001) sync mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x002) bist counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x003) bist result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0xn00) start update hold-off counter . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn01) nco control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn02) nco frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn03) nco frequency update hold-off counter . . . . . . . . . . . . . . . . . 39 (0xn04) nco phase offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn05) nco phase offset update hold-off counter . . . . . . . . . . . . . . . 39 (0xn06) cic scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn07) cic2 decimation ?1 (m cic2 ?1) . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn08) cic2 interpolation ?1 (l cic2 ?1) . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn09) cic5 interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0a) number of rcf coefficients ?1 . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0b) rcf coefficient offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0c) channel mode control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0d) channel mode control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn0e) fine scale factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn0f) rcf time slot sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn10?xn11) rcf phase equalizer coefficients . . . . . . . . . . . . . . . . . . . 40 (0xn12?xn15) fir-psk magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn16) serial port setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn17) power ramp length 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn18) power ramp length 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn19) power ramp rest time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn20?xn1f) unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn20?xn3f) data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn40?xn17f) power ramp coefficient memory . . . . . . . . . . . . . . . . . . 40 (0xn80?xnff) coefficient memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 write pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 read pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AD6623 evaluation pcb and software . . . . . . . . . . . . . . . . . . . . 41 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 u sing the AD6623 to p rocess umts c arriers . . . . . . . . . . . . . . . . . . . . . . 42 d igital-to-analog converter (d ac) s election . . . . . . . . . . . . . . . . . . . . . . 42 multiple tsp operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 determining the number of tsps to use . . . . . . . . . . . . . . . . . . . . . . . . . 42 programming multiple tsps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 driving multiple tsp serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 using the AD6623 to process two umts carriers with 24 output rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 configuring the AD6623 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AD6623 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
rev. a AD6623 ? product description the AD6623 is a 4-channel transmit signal processor (tsp) that creates high bandwidth data for transmit digital-to-analog converters (txdacs) from baseband data provided by a digi- tal signal processor (dsp). modern txdacs have achieved sufficiently high sampling rates, analog bandwidth, and dynamic range to create the first intermediate frequency (if) directly. the AD6623 synthesizes multicarrier and multistandard digital signals to drive these txdacs. the ram-based architecture allows easy reconfiguration for multimode applications. modula- tion, pulse-shaping and anti-imaging filters, static equalization, and tuning functions are combined in a single, cost-effective device. digital if signal processing provides repeatable manu- facturing, higher accuracy, and more flexibility than comparable high dynamic range analog designs. the AD6623 has four identical digital tsps complete with synchronization circuitry and cascadable wideband channel summation. AD6623 is pin compatible to ad6622 and can operate in ad6622-compatible control register mode. the AD6623 utilizes a 3.3 v i/o power supply and a 2.5 v core power supply. all i/o pins are 5 v tolerant. all control registers and coefficient values are programmed through a generic micro- processor interface. intel and motorola microprocessor bus modes are supported. all inputs and outputs are lvcmos compatible. functional overview each tsp has five cascaded signal processing elements: a programmable interpolating ram coefficient filter (rcf), a programmable scale and power ramp, a programmable fifth order cascaded integrator comb (cic5) interpolating filter, a flexible second order resampling cascaded integrator comb filter (rcic2), and a numerically controlled oscillator/tuner (nco). the outputs of the four tsps are summed and scaled on-chip. in multicarrier wideband transmitters, a bidirectional bus allows the parallel (wideband) if input/output to drive a second dac. in this operational mode two AD6623 channels drive one dac and the other two AD6623 channels drive a second dac. multiple AD6623s may be combined by driving the in out[17:0] of the succeeding with the out[17:0] of the preceding chip. the inout[17:0] can alternatively be masked off by software to allow preceding AD6623? outputs to be ignored. each channel accepts input data from independent serial ports that may be connected directly to the serial port of digital sig- nal processor (dsp) chips. the rcf implements any one of the following functions: inter- polating finite impulse response (fir) filter, /4-dqpsk modulator, 8-psk modulator, or 3 /8-8-psk modulator, gmsk modulator, and qpsk modulator. each AD6623 channel can be dynamically switched between the gmsk modulation mode and the 3 /8-8-psk modulation mode in order to support the gsm/edge standard. the rcf also implements an allpass phase equalizer (ape) which meets the requirements of is-95-a/b standard (cdma transmission). the programmable scale and power ramp block allows power ramping on a time-slot basis as specified for some air-interface standards (e.g., gsm, edge). a fine scaling unit at the pro- grammable fir filter output allows an easy signal amplitude level adjustment on time slot basis. the cic5 provides integer rate interpolation from 1 to 32 and coarse anti-image filtering. the rcic2 provides fractional rate interpolation from 1 to 4096 in steps of 1/512. the wide range of interpolation factors in each cic filter stage and a highly flexible resampler incorporated into rcic2 makes the AD6623 useful for creating both narrowband and wideband carriers in a high-speed sample stream. the high resolution 32-bit nco allows flexibility in frequency planning and supports both digital and analog air interface standards. the high speed nco tunes the interpolated complex signal from the rcic2 to an if channel. the result may be real or complex. multicarrier phase synchronization pins and phase offset registers allow intelligent management of the relative phase of independent rf channels. this capability supports the requirements for phased array antenna architectures and man- agement of the wideband peak/power ratio to minimize clipping at the dac. the wideband output ports can deliver real or complex data. complex words are interleaved into real (i) and imaginary (q) parts at half the master clock rate.
rev. a ? AD6623 recommended operating conditions test AD6623 parameter level min typ max unit vdd iv 2.25 2.5 2.75 v vddio iv 3.0 3.3 3.6 v t ambient iv ?0 +25 +85 c electrical characteristics parameter (conditions) temp test level min typ max unit logic inputs (5 v tolerant) logic compatibility full 3.3 v cmos logic ??voltage full iv 2.0 5.0 v logic ??voltage full iv ?.3 +0.8 v logic ??current full iv 1 10 a logic ??current full iv 0 10 a input capacitance 25 cv 4 pf logic outputs logic compatibility full 3.3 v cmos/ttl logic ??voltage (i oh = 0.25 ma) full iv 2.0 vdd ?0.2 v logic ??voltage (i ol = 0.25 ma) full iv 0.2 0.4 v idd supply current gsm example: core v 232 ma i/o 56 ma is-136 example: core v 207 ma i/o 55 ma wbcdma example v tbd ma sleep mode full iv tbd ma power dissipation gsm example v 740 mw is-136 example v 700 mw wbcdma example v tbd mw sleep mode full iv tbd mw see the thermal management section of the data sheet for further details. AD6623?pecifications
rev. a ? AD6623 general timing characteristics 1, 2 test AD6623as parameter (conditions) temp level min typ max unit clk timing requirements: t clk clk period full i 9.6 ns t clkl clk width low full iv 3 ns t clkh clk width high full iv 3 0.5 t clk ns reset timing requirement: t resl reset width low full i 30.0 ns input data timing requirements: t si inout[17:0], qin to clk setup time full iv 1 ns t hi inout[17:0], qin to clk hold time full iv 2 ns output data timing characteristics: t do clk to out[17:0], inout[17:0], qout output delay time full iv 2 6 ns t dzo oen high to out[17:0] active full iv 3 7.5 ns sync timing requirements: t ss sync(0, 1, 2, 3) to clk setup time full iv 1 ns t hs sync(0, 1, 2, 3) to clk hold time full iv 2 ns master mode serial port timing requirements (scs = 0): switching characteristics 3 t dsclk1 clk to sclk delay (divide by 1) full iv 4 10.5 ns t dsclkh clk to sclk delay (for any other divisor) full iv 5 13 ns t dsclkl clk to sclk delay (divide by 2 or even number) full iv 3.5 9 ns t dsclkll clk to sclk delay (divide by 3 or odd number) full iv 4 10 ns channel is self-framing t ssdi0 sdin to sclk setup time full iv 1.7 ns t hsdi0 sdin to sclk hold time full iv 0 ns t dsfo0a sclk to sdfo delay full iv 0.5 3.5 ns channel is external-framing t ssfi0 sdfi to sclk setup time full iv 2 ns t hsfi0 sdfi to sclk hold time full iv 0 ns t ssdi0 sdin to sclk setup time full iv 2 ns t hsdi0 sdin to sclk hold time full iv 0 ns t dsfo0b sclk to sdfo delay full iv 0.5 3 ns slave mode serial port timing requirements (scs = 1): switching characteristics 3 t sclk sclk period full iv 2 t clk ns t sclkl sclk low time full iv 3.5 ns t sclkh sclk high time full iv 3.5 ns channel is self-framing t ssdh sdin to sclk setup time full iv 1 ns t hsdh sdin to sclk hold time full iv 2.5 ns t dsfo1 sclk to sdfo delay full iv 4 10 ns channel is external-framing t ssfi1 sdfi to sclk setup time full iv 2 ns t hsfi1 sdfi to sclk hold time full iv 1 ns t ssdi1 sdin to sclk setup time full iv 1 ns t hsdi1 sdin to sclk hold time full iv 2.5 ns t dsfo1 sclk to sdfo delay full iv 10 ns notes 1 all timing specifications valid over vdd range of 2.375 v to 2.675 v and vddio range of 3.0 v to 3.6 v. 2 c load = 40 pf on all outputs (unless otherwise specified). 3 the timing parameters for sclk, sdin, sdfi, sdfo, and sync apply to all four channels (a, b, c, and d). specifications subject to change without notice.
rev. a ? AD6623 microprocessor port timing characteristics 1, 2 test AD6623as parameter (conditions) temp level min typ max unit microprocessor port, mode inm (mode = 0) mode inm write timing : t sc control 3 to clk setup time full iv 4.5 ns t hc control 3 to clk hold time full iv 2.0 ns t hwr wr( rw ) to rdy( dtack ) hold time full iv 8.0 ns t sam address/data to wr (rw) setup time full iv 3.0 ns t ham address/data to rdy( dtack ) hold time full iv 2.0 ns t drdy wr (rw) to rdy( dtack ) delay full iv 4.0 ns t acc wr (rw) to rdy( dtack ) high delay full iv 4 t clk 5 t clk 9 t clk ns mode inm read timing : t sc control 3 to clk setup time full iv 4.5 ns t hc control 3 to clk hold time full iv 2.0 ns t sam address to rd ( ds ) setup time full iv 3.0 ns t ham address to data hold time full iv 2.0 ns t zoz data three-state delay full iv ns t dd rdy( dtack ) to data delay full iv ns t drdy rd ( ds ) to rdy( dtack ) delay full iv 4.0 ns t acc rd ( ds ) to rdy( dtack ) high delay full iv 8 t clk 10 t clk 13 t clk ns microprocessor port, motorola (mode = 1) mode mnm write timing : t sc control 3 to clk setup time full iv 4.5 ns t hc control 3 to clk hold time full iv 2.0 ns t hds ds ( rd ) to dtack (rdy) hold time full iv 8.0 ns t hrw rw( wr ) to dtack (rdy) hold time full iv 8.0 ns t sam address/data to rw( wr ) setup time full iv 3.0 ns t ham address/data to rw( wr ) hold time full iv 2.0 ns t ddtack ds ( rd ) to dtack (rdy) delay ns t acc rw( wr ) to dtack (rdy) low delay full iv 4 t clk 5 t clk 9 t clk ns mode mnm read timing : t sc control 3 to clk setup time full iv 4.0 ns t hc control 3 to clk hold time full iv 2.0 ns t hds ds ( rd ) to dtack (rdy) hold time full iv 8.0 ns t sam address to ds ( rd ) setup time full iv 3.0 ns t ham address to data hold time full iv 2.0 ns t zd data three-state delay full iv ns t dd dtack (rdy) to data delay full iv ns t ddtack ds ( rd ) to dtack (rdy) delay full iv ns t acc ds ( rd ) to dtack (rdy) low delay full iv 8 t clk 10 t clk 13 t clk ns notes 1 all timing specifications valid over vdd range of 2.375 v to 2.675 v and vddio range of 3.0 v to 3.6 v. 2 c load = 40 pf on all outputs (unless otherwise specified). 3 specification pertains to control signals: rw, ( wr ), ds , ( rd ), cs . specifications subject to change without notice.
rev. a AD6623 ? timing diagrams clk t do t clk t clkl t clkh t zo t zo oen inout[17:0] out[17:0] qout figure 1. parallel output switching characteristics clk t si t hi inout[17:0] qin figure 2. wideband input timing clk sync t ss t hs figure 3. sync timing inputs r eset t resl figure 4. reset timing requirements clk sclk t dsclkh t sclkh t sclkl figure 5. sclk switching characteristics (divide by 1) clk sclk t dsclkh t dsclkl figure 6. sclk switching characteristic (divide by 2 or even integer) clk sclk t dsclkh t dsclkll figure 7. sclk switching characteristic (divide by 3 or odd integer)
rev. a AD6623 ? t dsfo0a t ssdi0 t hsdi0 sclk sdfo sdin datan figure 8. serial port timing, master mode (scs = 0), channel is self-framing t dsfo1 t hsdi1 sclk sdfo sdin datan t ssdi1 figure 9. serial port timing, slave mode (scs = 1), channel is self-framing t dsfo0b datan sdin sclk sdfo t ssdi0 t hsfi0 t ssfi0 nclks sdfi t hsdi0 figure 10. serial port timing, master mode (scs = 0), channel is external-framing t dsfo1 t hsdi1 datan sdin sclk sdfo t hsfi1 t ssfi1 nclks sdfi t ssdi1 figure 11. serial port timing, slave mode (scs = 1), channel is external-framing
rev. a AD6623 ? timing diagrams?nm microport mode clk rd ( ds ) wr (rw) cs a[2:0] d[7:0] rdy ( dtack ) t sc t hc t hwr t sam t sam t ham t drdy va l i d data va lid address t ham t acc notes 1. t acc access time depends on the address accessed. access time is measured from fe of wr to the re of rdy. 2. t acc requires a maximum 9 clk periods. figure 12. inm microport write timing requirements clk rd ( ds ) wr (rw) a[2:0] d[7:0] rdy ( dtack ) t sc t sam t zd t drdy va l id data va lid address t acc t hc cs t zd t ham notes 1. t acc access time depends on the address accessed. access time is measured from fe of wr to the re of rdy. 2. t acc requires a maximum of 13 clk periods and applies to a [ 2:0 ] = 7, 6, 5, 3, 2, 1 t dd figure 13. inm microport read timing requirements timing diagrams?nm microport mode clk ds ( rd ) cs a[2:0] d[7:0] dtack (rdy) t sc t hc t hrw t sam t sam t ham va l i d data va lid address t ham t acc notes 1. t acc access time depends on the address accessed. access time is measured from fe of ds to the fe of dtack . 2. t acc requires a maximum 9 clk periods. rw ( wr ) t ddtack t hds figure 14. mnm microport write timing requirements clk ds ( rd ) rw ( wr ) a[2:0] d[7:0] dtack ( rdy) t sc t sam t zd va l id data va lid address t acc t hc cs t zd t ham t dd t ddtack t hds notes 1. t acc access time depends on the address accessed. access time is measured from fe of ds to the fe of dtack . 2. t acc requires a maximum 13 clk periods. figure 15. mnm microport read timing requirements
rev. a AD6623 ?0 ordering guide model temperature range package description package option AD6623as ?0 c to +85 c (ambient) 128-lead mqfp (plastic quad flatpack) s-128 AD6623abc ?0 c to +85 c (ambient) 196-lead cspbga (chip scale package ball grid array) bc-196 AD6623s/pcb mqfp evaluation board with AD6623 and software AD6623bc/pcb cspbga evaluation board with AD6623 and software absolute maximum ratings * vddio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.6 v vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +2.75 v input voltage . . . . . . . . . . . . . . ?.3 v to +5 v (5 v tolerant) output voltage swing . . . . . . . . . . ?.3 v to vddio + 0.3 v load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf junction temperature under bias . . . . . . . . . . . . . . . . . 125 c operating temperature . . . . . . . . . ?0 c to +85 c (ambient) storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280 c * stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 128-lead mqfp with internal heat spreader: ja = 28.1 c/w, no airflow ja = 22.6 c/w, 200 lfpm airflow ja = 20.5 c/w, 400 lfpm airflow 196-lead bga: ja = 26.3 c/w, no airflow ja = 22 c/w, 200 lfpm airflow thermal measurements made in the horizontal position on a 4-layer board. explanation of test levels i. 100% production tested ii. 100% production tested at 25 c, and sample tested at specified temperatures iii. sample tested only iv. parameter guaranteed by design and analysis v. parameter is typical value only warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD6623 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a AD6623 ?1 pin configuration 128-lead mqfp 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 10 0 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 12 8 119 111 118 117 116 115 114 113 112 110 109 108 10 7 10 6 10 5 10 4 10 3 top view (not to scale) sdfic gnd sdfib sdfob sclkb sdina sdfoa sclka tdi tdo tms sdfia vdd gnd d4 d3 d2 d1 vddio vdd d0 ds(rd) dtack (rdy) rw( wr ) gnd gnd gnd mode a2 a1 a0 gnd tck trst gnd gnd inout0 gnd gnd inout1 inout2 inout3 inout4 vddio inout11 inout12 vddio inout13 inout14 inout15 inout16 sync3 gnd oen gnd gnd gnd out0 out1 gnd out3 out4 out5 out6 vddio out7 out8 out9 out10 gnd gnd gnd out11 out12 out13 out14 vddio out15 out16 out17 qout gnd gnd gnd gnd gnd gnd d6 d7 out2 vdd cs reset sync0 sync1 gnd gnd gnd inout17 inout5 inout6 inout7 inout8 gnd gnd gnd inout9 inout10 AD6623 qin sync2 gnd clk vdd gnd d5 gnd vddio sdfid sdind sdfod sclkd vddio sdinc sdfoc sdinb sclkc vdd gnd
rev. a AD6623 ?2 128-lead function descriptions pin number mnemonic type description 1, 3?, 9, 19?1, 31, 32, 34?6, 38, 39, gnd p ground connection 42, 52?4, 64?5, 68, 72, 83?5, 95, 96, 98, 99, 102, 103, 116, 128 2 oen 1 ia ctive high output enable pin 29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15, out[17:0] o/t parallel output data 13, 12, 11, 10, 8, 7, 6 47, 59, 66, 104, 127 vdd p 2.5 v supply 14, 26, 41, 78, 90, 110, 122 vddio p 3.3 v supply 30 qout o/t when high indicates q output data (complex output mode) 33, 37, 40, 43, 44, 45, 46, 48 d[7:0] i/o/t b idirectional microport data 49 ds ( rd )i inm mode: read signal, mnm mode: data strobe signal 50 dtack (rd y) o acknowledgment of a completed transaction (signals when p port is ready for an access) open drain, must be pulled up externally 51 rw ( wr )i active high read, active low write 55 mode i sets microport mode: mode = 1, mnm mode; mode = 0, i nm mode 56, 57, 58 a[2:0] i microport address bus 60 cs ic hip select, active low enable for p access 61 reset 2 ia ctive low reset pin 62 sync0 1 is ync signal for synchronizing multiple AD6623s 63 sync1 1 is ync signal for synchronizing multiple AD6623s 67 clk 1 i input clock 69 sync2 1 is ync signal for synchronizing multiple AD6623s 70 qin 1 i when high indicates q input data (complex input mode) 71, 74?7, 79?2, 86?9, 91?4, 97 inout[17:0] 1 i/o wideband input/output data (allows cascade of multiple AD6623 chips in a system) 73 sync3 1 is ync signal for synchronizing multiple AD6623s 100 trst 2 it est reset pin 101 tck 1 it est clock input 105 sdfia i serial data frame input?hannel a 106 tms 2 it est mode select 107 tdo o test data output 108 tdi 1 it est data input 109 sclka i/o bidirectional serial clock?hannel a 111 sdfoa o serial data frame sync output?hannel a 112 sdina 1 i serial data input?hannel a 113 sclkb i/o bidirectional serial clock?hannel b 114 sdfob o serial data frame sync output?hannel b 115 sdfib i serial data frame input ?hannel b 117 sdfic i serial data frame input?hannel c 118 sdinb 1 i serial data input?hannel b 119 sclkc i/o bidirectional serial clock?hannel c 120 sdfoc o serial data frame sync output?hannel c 121 sdinc 1 i serial data input?hannel c 123 sclkd i/o bidirectional serial clock?hannel d 124 sdfod o serial data frame sync output?hannel d 125 sdind 1 i serial data input?hannel d 126 sdfid i serial data frame input?hannel d notes 1 pins with a pull-down resistor of nominal 70 k ? . 2 pins with a pull-up resistor of nominal 70 k ? .
rev. a AD6623 ?3 pin configuration 196-lead cspbga a b c d e f g h j k l m n p nc = no connect 1 nc out2 out5 out8 out9 out11 out14 out16 qout nc 2 out1 out4 out7 out10 out13 d6 3 out0 out3 out6 out12 out17 out15 d7 4 sdfid oen sdfod d4 d5 d2 5 sdinc sdind vddio vdd vddio vdd vddio vdd d1 d3 6 sdinb sdfoc sclkd vdd gnd gnd gnd gnd vddio dtack ( rdy) d0 7 sdfob sdfic sclkc vddio gnd gnd gnd gnd vdd mode ( ale) rw ( wr) 8 sclkb sdina sdfib vdd gnd gnd gnd gnd vddio a1 9 sclka tdi sdfoa vddio gnd gnd gnd gnd vdd reset a0 a2 10 tdo tms vdd vddio vdd vddio vdd vddio sync0 cs 11 sdfia trst sync1 12 tck in2 in3 in6 in12 in16 qin 13 in5 in8 in11 in14 in17 clk 14 nc in0 in1 in4 in7 in9 in10 in13 in15 sync3 sync2 nc ba ll legend i/o ground core power ring power 15mm sq. 1.0mm a b c d e f g h j k l m n p 12345678910 11 12 13 14 top view ds ( rd)
rev. a AD6623 ?4 196-lead function descriptions mnemonic type function power supply vdd p 2.5 v supply vddio p 3.3 v io supply gnd g ground inputs inout[17:0] 1 i/o a input data (mantissa) qin 1 iw hen high indicates q input data (complex input mode) reset 2 ia ctive low reset pin clk 1 i input clock sync0 1 ia ll sync pins go to all four output channels sync1 1 ia ll sync pins go to all four output channels sync2 1 ia ll sync pins go to all four output channels sync3 1 ia ll sync pins go to all four output channels sdina 1 i serial data input?hannel a sdinb 1 i serial data input?hannel b sdinc 1 i serial data input?hannel c sdind 1 i serial data input?hannel d cs ia ctive low chip select control sclka i/o bidirectional serial clock?hannel a sclkb i/o bidirectional serial clock?hannel b sclkc i/o bidirectional serial clock?hannel c sclkd i/o bidirectional serial clock?hannel d sdfoa o serial data frame sync output?hannel a sdfob o serial data frame sync output?hannel b sdfoc o serial data frame sync output?hannel c sdfod o serial data frame sync output?hannel d sdfia i serial data frame input?hannel a sdfib i serial data frame input?hannel b sdfic i serial data frame input?hannel c sdfid i serial data frame input?hannel d oen 1 ia ctive high output enable pin microport control d[7:0] i/o/t bidirectional microport data a[2:0] i microport address bus ds ( rd )i active low data strobe (active low read) dtack (rdy) 2 o/t active low data acknowledge (microport status bit) rw ( wr )i read write (active low write) mode i intel or motorola mode select outputs out[17:0] o wideband output data qout o when high indicates q output data (complex output mode) jtag and bist trst 2 it est reset pin (active low) tck 1 it est clock input tms 2 it est mode select input tdo o/t test data output tdi 1 it est data input notes 1 pins with a pull-down resistor of nominal 70 k ? . 2 pins with a pull-up resistors of nominal 70 k ? .
rev. a AD6623 ?5 control register address notation register address notation and bit assignment referred to throughout this data sheet are as follows: there are eight, one-digit ?xternal register addresses in decimal format. ?nternal?address notation (read from left to right) begins with ?x? meaning the address that follows is hexadecimal. the next three characters represent the address. the first number or character is the msb of the address. if an ??is present, its value can be 1, 2, 3, or 4 and it depends upon the channel that is being addressed (a, b, c, or d). the remaining two digits preceding the colon (if present) are the lsbs of the address. if a colon follows the address, then the succeeding digits tell the user what bit number(s) is/are involved in decimal format. for example, 0xn24:7-0. serial data port the AD6623 has four independent serial ports (a, b, c, and d), and each accepts data to its own channel (a, b, c, or d) of the device. each serial port has four pins: sclk (serial clock), sdfo (serial data frame out), sdfi (serial data frame in), and sdin (serial data input). sdfi and sdin are inputs, sdfo is an output, and sclk is either input or output depending on the state of scs (serial clock slave: 0xn16, bit 4). each channel can be oper ated either as a master or slave channel depending upon scs. the serial port can be self-framing or accept external framing from the sfdi pin or from the previous adjacent channel (0xn16, bits 7 and 6). serial master mode (scs = 0) in master mode, sclk is created by a programmable internal counter that divides clk. when the channel is ?leeping,?sclk is held low. sclk becomes active on the first rising edge of clk after channel sleep is removed (d0 through d3 of external address 4). once active, the sclk frequency is determined by the clk frequency and the sclk divider, according to the equations below. AD6623 mode: f f sclkdivider sclk clk = + 1 (1) ad6622 mode: f f sclkdivider sclk clk = + 21 () (2) the sclk divider is a 5-bit unsigned value located at internal channel address 0xn0d (bits 4?), where ??is 1, 2, 3, or 4 for the chosen channel a, b, c, or d, respectively. the user must select the sclk divider to insure that sclk is fast enough to accept full input sample words at the input sample rate. see the design example at the end of this section. the maximum sclk frequency is equal to the clk when operating in AD6623 mode serial clock master. when operating in ad6622 compatible mode, the maximum sclk frequency is one-half the clk. the minimum sclk frequency is 1/32 of the clk frequency in AD6623 mode or 1/64 of the clk frequency when in ad6622 mode. sdfo changes on the positive edge of sclk when in master mode. sdin is captured on positive edge when sclk is in master mode. serial slave mode (scs = 1) any of the AD6623 serial ports may be operated in the serial slave mode. in this mode, the selected AD6623 channel requires that an external device such as a dsp to supply the sclk. this is done to synchronize the serial port to meet an external timing requirement. sdin is captured on negative edge of sclk when in slave mode. serial data framing the sdin input pin of each transmit channel of the AD6623 receives data from an external dsp to be digitally filtered, inter- polated, and then modulated by the nco-generated carrier. serial data from the dsp to the AD6623 is sent as a series of blocks or frames. the length of each block is a function of the desired output format that is supported by the AD6623. block length may range from 1 bit (msk) to 32 bits of i and q data. the flow of data to the sdin input is regulated either by the AD6623 (in self-framing mode) or by the external dsp (using AD6623 external framing mode). this is accomplished by generating a pulse, sdfo or sdfi, to indicate that the next frame or serial data block is ready to be input or sent to the AD6623. functions of the two pins, sdfo and sdfi, are fully described in the framing modes that follow. self-framing mode in this mode bit 7 of register 0xn16 is set low. the serial data frame output, sdfo, generates a self-framing data request and is pulsed high for one sclk cycle at the input sample rate. in this mode, the sdfi pin is not used, and the sdfo signal would be programmed to be a serial data frame request (0xn16, bit 5 = 0). sdfo is used to provide a sync signal to the host. the input sample rate is determined by the clk divided by channel interpo- lation factor. if the sclk rate is not an integer multiple of the input sample rate, then the sdfo will continually adjust the period by one sclk cycle to keep the average sdfo rate equal to the input sample rate. when the channel is in sleep mode, sdfo is held low. the first sdfo is delayed by the chan nel reset latency after the channel reset is removed. the channel reset latency varies dependent on channel configuration. external framing mode in this mode bit 7 of register 0xn16 is set high. the external framing can come from either the sdfi pin (0xn16, bit 6 = 0) or the previous adjacent channel (0xn16, bit 6 = 1). in the case of external framing from a previous channel, it uses the internal frame end signal for serial data frame synchronizing. when in master mode, sdfo and sdfi transition on the positive edge of sclk, and sdin is captured on the positive edge of sclk. when in slave mode, sdfo and sdfi transition on the negative edge of sclk, and sdin is captured on the negative edge of sclk. serial port cascade configuration in this case the sdfo signal from the last channel of the first chip would be programmed to be a serial data frame end (sfe:0xn16, bit 5 = 1). this sdfo signal would then be fed as an input for the second cascaded chip? sdfi pin input. the second chip would be programmed to accept external framing from the sdfi pin (0xn16, bit 7 = 1, bit 6 = 0).
rev. a AD6623 ?6 see table ii for usable sclk divider values and the corre- sponding sclk and f sclk /f sdfo ratio for the example of l = 2560. in conclusion, sdfo rate is determined by the AD6623 clk rate and the interpolation rate of the channel. the sdfo rate is equal to the channel input rate. the channel interpolation is equal to rcf interpolation times cic5 interpolation, times cic2 interpolation: ll l l m rcf cic cric cric = ? ? ? ? ? ? 5 2 2 (4) the sclk divide ratio is determined by sclkdivider as shown in equation 3. the sclk must be fast enough to input 32 bits of data prior to the next sdfo. extra sclks are ignored by the serial port. table ii. example of usable sclk divider values and f sclk /f sdfo ratios for l = 2560 sclkdivider f sclk /f sdfo 0 2560 1 1280 3 640 4 512 7 320 9 256 15 160 19 128 31 80 programmable ram coefficient filter (rcf) each channel has a fully independent ram coefficient filter (rcf). the rcf accepts data from the serial port, processes it, and passes the resultant i and q data to the cic filter. a variety of processing options may be selected individually or in combination, including psk and msk modulation, fir filtering, all-pass phase equalization, and scaling with arbitrary ramping. see table iii. table iii. data format processing options processing block input data output data interpolating fir filter i and q i and q psk modulator 2 or 3 bits per symbol unfiltered i and q: /4-qpsk, 8-psk, or 3 /8-8-psk msk modulator 1 bit per symbol filtered msk or gsm i and q qpsk 2 bits per symbol filtered qpsk i and q all-pass phase equalizer i and q i and q scale and ramp i and q i and q serial data format the format of data applied to the serial port is determined by the rcf mode selected in control register 0xn0c. below is a table showing the rcf modes and input data format that it sets. table i. serial data format 0xn0c 0xn0c 0xn0c serial data rcf bit 6 bit 5 bit 4 word length mode 0 0032 fir 00 1 /4-dqpsk 01 0 gmsk 01 1 msk 1 00 24 (bit 9 is high) fir, 16 (bit 9 is low) compact 10 1 8-psk 11 0 3 /8-8-psk 11 1 qpsk the serial data input, sdin, accepts 32-bit words as channel input data. the 32-bit word is interpreted as two 16-bit two? comple- ment quadrature words, i followed by q, msb first. this results in linear i and q data being provided to the rcf. the first bit is shifted into the serial port starting on the next rising edge of sclk after the sdfo pulse. figure 16 shows a timing diagram for sclk master (scs = 0) and sdfo set for frame request (sfe = 0). t dsdfo0a t hsdi0 sclk sdfo sdi datan clk t ssdi0 clkn t ssdi0 figure 16. serial port switching characteristics as an example of the serial port operation, consider a clk frequency of 62.208 mhz and a channel interpolation of 2560. in that case, the input sample rate is 24.3 ksps (62.208 mhz/2560), which is also the sdfo rate. substituting, f sclk 32 3 f sdfo into the equation and solving for sclkdivider, we find the minimum value for sclkdivider according to the equation below. sclkdivider f f clk sdfo 32 (3) evaluating this equation for our example, sclkdivider must be less than or equal to 79. since the sclkdivider channel register is a 5-bit unsigned number it can only range from 0 to 31. any value in that range will be valid for this example, but if it is important that the sdfo period is constant, then there is another restric- tion. for regular frames, the ratio f sclk /f sdfo must be equal to an integer of 32 or larger. for this example, constant sdfo periods can only be achieved with an sclk divider of 31 or less.
rev. a AD6623 ?7 overview of the rcf blocks the serial port passes data to the rcf with the appropriate format and bit precision for each rcf configuration, see figure 17. the data may be modulated vectors or unmodulated bits. i and q vectors are sent directly to the interpolating fir filter. unmodulated bits may be sent to the psk modulator, the interpolating msk modulator, or the interpolating qpsk modulator. the psk modulator produces unfiltered i and q vectors at the symbol rate which are then passed through the interpolating fir filter. the interpolating msk modulator and the interpolating qpsk modulator produce oversampled, pulse-shaped vectors directly without employing the interpolating fir filter. when possible, the msk and qpsk modulators are recommended for increased throughput and decreased power consumption compared to interpolating fir filter. in addition, the interpolating msk modulator can realize filters with nonlinear inter-symbol inter- ference, achieving excellent accuracy for gmsk applications. after interpolation, an optional allpass phase equalizer (ape) can be inserted into the signal path. the ape can realize any real, stable, two-pole, two-zero all-pass filter at the rcf? interpolated rate. this is especially useful to precompensate for nonlinear phase responses of receive filters in terminals, as specified by is-95. when active, the ape utilizes shared hardware with the interpo- lating modulators and filter, which may reduce the allowed rcf throughput, inter-symbol interference, or both. see figure 18. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 bit < msb, i, lsb > < msb, q, lsb > fir 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876 543210 bit < msb, i, lsb > < msb, q, lsb > compact fir 15 14 13 12 11 10 9876543210 bit < msb, i, lsb > < msb, q, lsb > compact fir 43210 bit ms d1 d2 d0 8psk 43210 bit serial sync msxd1d 0q psk ramp 43210 bit msxxd0 msk/gsm 210 bit 0d 1d 0 8psk 10 bit d1 d0 qpsk 0bit d0 msk/gsm these three formats are av ailable only when serial time slot sync enable cont. reg. 0xn16:2 = 1 and ignored in fir mode these three formats are ava ilable only when serial time slot sync enable cont. reg. 0xn16:2 = 0 and ignored in fir mode m = mode bit. if m = 0, then the msb of 3-bit mode select word at 0xn0c:6 is set to 0 (this is also called mode 0). if m = 1, then the msb is set to 1 and this is mode 1. mode allows quick format changes via the serial port, for example, 010 = gmsk and 110 = 3pi/8psk. the value m should be held for the duration of the time slot since the value of m will only be updated after the rcf scale holdoff counter reaches a value of 1 (see below). s = serial time slot sync bit. if s = 0, then no sync is generated. if s = 1, a ?erial time slot sync?occurs that loads the rcf scale hold-off counter with a user programmed value and commences a backwards count of clk cycles. when the counter reaches one, an automatic sequence occurs as f ollows: power ramp down occurs, m (above) is updated, serial input is suspended for a rest or quiet time and any control register with a 2 supersc ript is updated. after rest, the serial input becomes active and the power level is ramped up to the fine scale multiplier value or any lesser power level. ram p enable bit, 0xn16:0, must be set to logic 1 for the ramp functions to occur. see the rcf power ramping and time slot synchronization sections for more detail. x = don? care d = payload data bit important notes: the sync pulse, s, should be held at logic 1 for only one serial frame since every frame with logic 1 in the s position will cause the rcf scale hold-off counter to reload its beginning count and begin counting again. the rcf scale hold-off counter counts master clk cycles. the r est time period is a programmable 5-bit v alue that counts interpolated rcf output samples before resuming serial input to the channel. the succeeding actions of any ho ld-off counter in the AD6623 can be defeat- ed b y settin g its count value to 0. figure 17. data formats supported by the AD6623 when sclk master (scs = 0), and sfdo set for frame request (sfe = 0)
rev. a AD6623 ?8 table iv. fir filter internal precision minimum maximum signal x y notation decimal hexadecimal (h) decimal hexadecimal (h) i and q inputs 1.15 ?.00000 +1.00000 0.999969 0.fffe coefficients 1.15 ?.00000 +1.00000 0.999969 0.fffe product 2.18 ?.99969 +3.00020 1.000000 1.00000 sum 4.18 ?.00000 +8.00000 7.999996 7.ffffc fir output 1.17 ?.00000 +1.00000 0.999992 0.ffff8 interpolating fir filter interpolating msk modulator interpolating qpsk modulator allpass phase equalizer psk modulator scale and ramp da ta from serial port data to cic filters figure 18. rcf block diagram the scale and ramp block adjusts the final magnitude of the modulated rcf output. a synchronization pulse from the sync0? pins or serial words can be used to command this block to ramp down, pause, and ramp up to a new scale factor. the shape of the ramp is stored in ram, allowing complete sample by sample control at the rcf interpolated rate. this is particularly useful for time division multiplexed standards such as gsm/edge. modulator configurations can be updated while the ramp is quiet, allowing for gsm and edge timeslots to be multiplexed together without resetting or reconfiguring the channel. each of the rcf processing blocks is discussed in greater detail in the following sections. interpolating fir filter the interpolating fir filter realizes a real, sum-of-products filter on i and q inputs using a single interleaved multiply-accumulator (mac) running at the clk rate. the input signal is interpolated by integer factors to produce arbitrary impulse responses up to 256 output samples long. each bus in the data path carries bipolar two? complement values. for the purpose of discussion, we will arbitrarily consider the radix point positioned so that the input data ranges from ? to just below 1. in figure 19, the data buses are marked x y to denote finite precision limitations. a bus marked x y has x bits above the radix and y bits below the radix, which implies a range from ? x? to 2 x? ?2 ? in 2 ? steps. the range limits are tabulated in table iv for each bus. the hexadecimal values are bit-exact and each msb has nega tive weight. note that the product bus range is limited by result of the multiplication and the two most significant bits are the same except in one case. dmem 32 16 cmem 256 16 input a ccumulator product 4.18 1.15 input 1.15 coef 1.15 2.18 1.17 output 2 0 , 2 ? , 2 ? , or 2 ? figure 19. interpolating fir filter block diagram the rcf realizes a fir filter with optional interpolation. the fir filter can produce impulse responses up to 256 output samples long. the fir response may be interpolated up to a factor of 256, although the best filter performance is usually achieved when the rcf interpolation factor (l rcf ) is confined to eight or below. the 256 16 coefficient memory (cmem) can be divided among an arbitrary number of filters, one of which is selected by the coefficient offset pointer (channel address 0x0b). the polyphase implementation is an efficient equivalent to an integer up-sampler followed fir filter running at the interpolated rate. the AD6623 rcf realizes a sum-of-products filter using a polyphase implementation. this mode is equivalent to an inter- polator followed by a fir filter running at the interpolated rate. in the functional diagram below, the interpolating block in- creases the rate by the rcf interpolation factor (l rcf ) by inserting l rcf ? zero valued samples between every input sam ple. the next block is a filter with a finite impulse response length (n rcf ) and an impulse response of h[n], where n is an integer from 0 to n rcf ?. the difference equation for figure 20 is written below, where h[n] is the rcf impulse response, b[n] is the interpolated input sample sequence at point ??in the diagram above, and c[n] is the output sample sequence at point ??in figure 20.
rev. a AD6623 ?9 n rcf ta p fir filter h[n] l rcf f in l rcf b a c f in f in l rcf figure 20. rcf interpolation cn hn bn k n rcf [] = [] [] = k 0 1 (5) this difference equation can be described by the transfer function from point ??to ??as: hz hnz bc k n rcf () = [] = 0 1 1 (6) the actual implementation of this filter uses a polyphase decom- position to skip the multiply-accumulates when b[n?] is zero. compared to the diagram above, this implementation has the benefits of reducing by a factor of l rcf both the time needed to calculate an output and the required data memory (dmem). the price of these benefits is that the user must place the coefficients into the coefficient memory (cmem) indexed by the interpolation phase. the process of selecting the coefficients and placing them into the cmem is broken into three steps shown below. the fir accepts two? complement i and q samples from the serial port with a fixed-point resolution of 16 bits each. when the serial port provides data with less precision, the lsbs are padded with zeroes. the data-mem stores the most recent 16 i and q pairs for a total of 32 words. the size of the data-mem limits the rcf impulse response to 16 l rcf output samples. when the data words from the serial port have fewer than 16 bits, the lsbs are padded with zeroes. the data-mem can be accessed through the microport from 0x20 to 0x5f above the processing channel? base internal address, while the channel? prog bit is set (external address 4). in order to avoid start-up transients, the data-mem should be cleared before operation. the prog bit must then be reset to enable normal operation. the coef-mem stores up to 256 16-bit filter coefficients. the coef- mem can be accessed through the microport from 0x800 to 0x8ff above the processing channel? base internal address, while the channel? prog bit is set (external address 4). for ad6622 compatibility, the lower 128 words are also mirrored from 0x080 to 0x0ff above the processing channel? base internal address, while the prog bit is set. there is a single multiply-accumulator (mac) on which both the i and q operations must be interleaved. two clk cycles are required for the mac to multiply each coefficient by an i and q pair. the mac is also used for four additional clk cycles if the all-pass phase equalizer is active. the size of the data-mem and coef-mem combined with the speed of the mac determine the total number of the taps per phase (t rcf ) that may be calculated. t rcf is the number of rcf input samples that influence each rcf output sample. the maximum available t rcf is calculated by the equation below. t least of floor l floor f f ape rcf rcf clk sdfo ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16 256 2 2 ,, (7) where ape = 1 (allpass phase equalizer enabled) or 0 (allpass phase equalizer disabled) and f sdfo = [output data rate/total interpolation rate] in hz. floor() ?indicates that the value within the parenthesis should be reduced to the lowest integer, e.g., floor(9.9999) = 9. the impulse response length at the output of the rcf is deter mined by the product of the number of interfering input samples (t rcf ) and the rcf interpolation factor (l rcf ), as shown by equation (8) below. the values of n rcf and t rcf are programmed into control registers. l rcf is not a control register, but n rcf and t rcf must be set so that l rcf is an integer. if the integer interpolation by the rcf results in an inconvenient sample rate at the output of the rcf, the desired output rate can usually be achieved by selecting non-integer interpolation in the resampling cic 2 filter. ntl rcf rcf rcf = (8)
rev. a AD6623 ?0 table v. channel a rcf control registers channel bit address width description 0x10a 16 15?: n rcf ? b; 7?: n rcf ? a 0x10b 8 7?: o rcf 0x10c 10 9: ch. a compact fir input word length 0: 16 bits? i followed by 8 q 1: 24 bits?2 i followed by 12 q 8: ch. a rcf prbs enable 7: ch a rcf prbs length 0: 15 1: 8,388,607 6?: ch. a rcf mode select 000 = fir 001 = /4-dqpsk modulator 010 = gmsk look-up table 011 = msk look-up table 100 = fir compact mode 101 = 8-psk 110 = 3 /8-8psk modulator 111 = qpsk look-up table 3?: ch. a rcf taps per phase 0x10d 8 7?: rcf coarse scale (g): 00 = 0 db 01 = ? db 10 = ?2 db 11 = ?8 db 5: ch. a allpass ph. eq. enable 4?: serial clock divider (1, ..., 32) 0x1 0e 16 15 2: ch. a unsigned scale factor 1?: reserved 0x10f 18 17?6: ch. a time slot sync select 00: sync0 (see 0x001 time slot) 01: sync1 10: sync2 11: sync3 15 0: ch. a rcf scale hold-off counter 1) ramp down (if ramp is enabled) 2) update scale and mode 3) ramp up (if ramp is enabled) 0x110 16 15?: ch. a rcf phase eq coef1 0x111 16 15?: ch. a rcf phase eq coef2 0x112 16 15?: ch. a rcf mpsk magnitude 0 0x113 16 15?: ch. a rcf mpsk magnitude 1 0x114 16 15?: ch. a rcf mpsk magnitude 2 0x115 16 15?: ch. a rcf mpsk magnitude 3 0x116 8 7: reserved 6: ch. a serial data frame select 0: serial data frame request 1: serial data frame end channel bit address width description 5: ch. a external sdfi select 0: internal sdfi 1: external sdfi 4: ch. a sclk slave select 0: master 1: slave 3: ch. a serial fine scale enable 2: ch. a serial time slot sync enable (ignored in fir mode) 1: ch. a ramp interpolation enable 0: ch. a ramp enable 0x117 6 5?: ch. a mode 0 ramp length, r0? 0x118 6 5?: ch. a mode 1 ramp length, r1? 0x119 5 4?: ch. a ramp rest time, q 0x11a?x11f r eserved 0x120?x13f 16 15?: ch. a data memory 0x140?x17f 16 15?4: reserved 13?: ch. a power ramp memory 0x180?x1ff 16 15?: ch. a coefficient memory this address is mirrored at 0x900?x97f and contiguously extended at 0x980?x9ff psk modulator the psk modulator is an AD6623 e xt ension feat ure that is only available when the control register bit 0x000:7 is high. the psk modulator creates 32-bit complex inputs to the interpolating fir filter from two or three data bits captured by the serial port. the fir filter operates exactly as if the 32- bit word came directly from the serial port. there are three psk modulation options to choose from: /4-dqpsk, 8- psk, and 3 /8-8-psk. every sy mbol of any of these modulations can be represented by one of the 16 phases shown in figure 21. 0 figure 21. 16-phase modulations
rev. a AD6623 ?1 all of these phase locations are represented in rectangular coor- dinates by only four unique magnitudes in the positive and negative directions. these four values are read from four channel registers that are programmed according to the following table, which gives the generic formulas and a specific example. the example is notable because it is only 0.046 db below full-scale and the 16-bit quantization is so benign at that magnitude, that the rms error is better than ?22 dbc. it is also worth noting that because none of the phases are aligned with the axes, magnitudes slightly beyond 0.16 db above full-scale are achievable. table vi. program registers channel register magnitude m magnitude e 0x7f53 0x12 m 3 cos( /16) 0x7ce1 0x13 m 3 cos(3 /16) 0x69de 0x14 m 3 cos(5 /16) 0x46bd 0x15 m 3 cos(7 /16) 0x18d7 using the four channel registers from the preceding table, the psk modulator assembles the 16 phases according to table vii. table vii. psk modulator phase phase i value q value 0 0x12 0x15 1 0x13 0x14 2 0x14 0x13 3 0x15 0x12 4 ?x15 +0x12 5 ?x14 +0x13 6 ?x13 +0x14 7 ?x12 +0x15 8 ?x12 ?x15 9 ?x13 ?x14 10 ?x14 ?x13 11 ?x15 ?x12 12 +0x15 ?x12 13 +0x14 ?x13 14 +0x13 ?x14 15 +0x12 ?x15 the following three sections show how the phase values are created for each psk modulation mode. /4-dqpsk modulation is-136 compliant /4-dqpsk modulation is selected by setting the channel register 0xn0c: 6? to 001b. the phase word is calculated according to the following diagram. the two lsbs of the serial input word update the payload bits once per symbol. the qpsk mapper creates a data dependent static phase word (sph) which is added to a time dependent rotating phase word (rph). the rph starts at zero when the rcf is reset or switches modes via a sync pulse. otherwise, the rph increments by two on every symbol. serial qpsk mapper sph [1:0] [3:0] phase [3:0] [3:0] rph 2 figure 22. qpsk mapper the sph word is calculated by the qpsk mapper according to the following truth table. table viii. qpsk mapper truth table serial [1:0] sph [3:0] 00b 0 01b 4 11b 8 10b 12 8-psk modulation is-136+ compliant 8-psk modulation is selected by setting the channel register 0xn0c: 6? to 101b. the phase word is calcu- lated according to the following diagram. the three lsbs of the serial input word update the payload bits once per symbol. serial 8-psk mapper [2:0] phase [3:0] figure 23. 8-psk mapper the phase word is calculated by the 8-psk mapper according to the following truth table: table ix. 8-psk mapper truth table serial [2:0] sph [3:0] 111b 0 011b 2 010b 4 000b 6 001b 8 101b 10 100b 12 110b 14 3 /8-8-psk modulation edge compliant 3 /8-8-psk modulation is selected by setting the channel register 0xn0c: 6? to 110b. the phase word is calcu lated according to the following diagram. the three lsbs of the serial input word update the payload bits once per symbol. the 8-psk mapper creates a data-dependent static phase word (sph) which is added to a time-dependent rotating phase word (rph). the 8-psk mapper operates exactly as described in the preceding 8-psk modulation section. the rph starts at zero when the rcf is reset or switches modes via a sync pulse. otherwise, the rph increments by three on every symbol.
rev. a AD6623 ?2 table x. coefficient weights register value coefficient weight 0x7fff +1.999938964844 .. 0x0001 +0.00006103515625 0x0000 0 0xffff 0.00006103515625 .. 0x8001 ?.999938964844 0x8000 ? table xi shows the recommended b 1 and b 2 coefficients for the respective oversampling rate. table xi. b 1 and b 2 coefficients over- sampling b 0 b 1 b 2 11 ?.25421 (0.efbbh) +0.11188 (0.0729h) 21 ?.96075 (0.c283h) +0.33447 (0.1568h) 31 ?.28210 (0.adf2h) +0.48181 (0.1ed6h) 41 ?.45514 (0.a2dfh) +0.57831 (0.2503h) 51 ?.56195 (0.9c09h) +0.64526 (0.294ch) 61 ?.63409 (0.976bh) +0.69415 (0.2c6dh) 71 ?.68604 (0.9418h) +0.73132 (0.2eceh) 81 ?.72516 (0.9197h) +0.76050 (0.30ach) fine scale and power ramp fine scale multiplier factors in the range [0, 2) with a step reso lution of 2 ?6 . power ramp multiplier factors in the range [0, 1) with a step resolution of 2 ?4 . fine scaling fine scale multiplier factors range from [0, 2) with a step reso lution of 2 ?5 in the ad6622 emulation mode and 2 ?6 in the AD6623 emulation mode. scaling values for each channel are pro- grammed at register 0xn0e in the AD6623 internal memory using the m icroport interface. rcf power ramping when the output of the AD6623 is programmed to be a rapid series of on/off bursts of data, the dac used to produce an analog output signal will produce undesirable spectral compo nents that should (or must) be suppressed. shaping or ?amping?the transition from no power to full power, and vice versa, reduces the amplitude of these spurious signals. to pro gram the ramp function a user must provide, through the microport, the ramp memory (rmem) coefficient values (up to 64), number of rmem coefficients to ?onstruct?the ramp (1 to 64) and selection of a synchronizing signal source as discussed below. the programmable power ramp up/down unit allows power ramping on time-slot basis as specified for some wireless transm ission technologies (e.g. tdma). the shape of the ramp is stored in ram. the ram coeffi cients (rmem) allow complete sample-by-sample control at the rcf interpolated rate. this is particularly useful for time division multiplexed standards such as gsm/edge. a time slot or ?urst?is ramped-up and down by multiplying the fine scaled output of the rcf by a series of up to 64 ramp coefficients. if more ramp resolution is required, up to 64 interpolated coefficients can be added if the ramp interpolation bit, 0xn16:1, is set to serial 8-psk mapper sph [2:0] [3:0] phase [3:0] [3:0] rph 3 figure 24. 3 /8-8-psk mapper msk look-up table the msk look-up table mode for the rcf is selected in control register 0xn0c. in the msk mode, the rcf performs arbitrary pulse-shaping based on four symbols of impulse response. f or the msk mode, the serial input format is 1 bit of data. gmsk look-up table the gmsk look-up table mode for the rcf is selected in control register 0xn0c. in the gmsk mode, the rcf performs arbitrary pulse-shaping based on four symbols of impulse response. f or the gmsk mode, the serial input format is 1 bit of data. qpsk look-up table the qpsk filter mode for the rcf is selected in control register 0xn0c. in the qpsk mode, the rcf performs baseband linear pulse-shaping based on filter impulse response up to 12 symbols. for the qpsk mode, the serial input format is 1 bit i followed by 1 bit q. phase equalizer the is-95 standard includes a phase equalizer after matched filtering at the baseband transmit side of a base station. this filter pre-distorts the transmitted signal at the base station in order to compensate for the distortion introduced to the received signal by the analog baseband filtering in a handset. the AD6623 includes this functionality in the form of an infinite impulse response (iir) all-pass filter in the rcf. this phase equalizer pre-distort filter has the following transfer function: hz yz xz bz b z zbzb () () () == ++ ++ 11 2 12 2 2 (9) z ? z ? z ? z ? x(z) y(z) b 2 b 1 figure 25. second order all-pass iir filter the allpass phase equalizer (ape) is enabled (logic 1) or dis abled (logic 0) in control register 0xn0d:5. the value of bit 5 then b ecomes the value of the ape term in equation 7. the coeffi cients b 1 and b 2 are located in control registers 0xn10 and 0xn11 respectively. the format for b 1 and b 2 is two? complement fractional binary with a range of [?, 2). with one bit for sign at most significant bit position there are 15 bits for magnitude. the value of one bit is (2 ?5 ) 2, or 0.00006103515625. the register values, in hexadecimal, and the corresponding coefficient weight from positive full-scale through zero to negative full-scale is illustrated in table x.
rev. a AD6623 ?3 logic 1. this extends the maximum ramp length to 128 coeffi- cients. although the ramp is limited in length, its time duration is a function of the output sample rate of the rcf multiplied by the ramp length. ramp duration is twice as long with ramp interpolation enabled than when it is not enabled. the channel? ramp enable bit at control register address 0xn16: bit 0, must be set to logic 1 or else the ramp function will be bypassed and the rcf output data is passed unaltered to the cic interpolation stages. when in use, the maximum signal gain is dependent on what value is stored in the last valid rmem (ramp memory) location. rmem words are 14-bits with a range of [0-1). when the ramp is triggered, the following sequence occurs (see figures 26 and 27): ramp-down beginning at the last coeffi cient of the specified ramp length and proceeding, sample- by- sample, to the first coefficient. next, a rest or quiet period (from 0 to 32 rcf output samples duration) occurs. during this time, the mode bit (as shown in figure 17, AD6623 data format and bit definition chart) is updated, input sampling is halted and any control register with a superscript 2 is updated. modulator configurations can be updated while the ramp is ?uiet?allowing for gsm and edge timeslots to be multiplexed without reset ting or reconfiguring the channel. lastly, ramp-up occurs beginning at the first coefficient and ending at the last coefficient of the specified length. the final output level from the ramp stage is equal to the rcf fine scale output level multiplied by the last ramp coefficient. figure 26. view of an unmodulated carrier with linear ramp-down and ramp-up and rest time between ramps set to 0. figure 27. view of an unmodulated carrier with linear ramp-down and ramp-up and rest time between ramps set to 30 (rcf output sample time periods) ramp triggering the ramp sequence is triggered by the fine scale hold-off counter. the counter is loaded with a 16-bit user-specified value (>1 and <2 16 ) upon receipt of a sync pulse. the counter then counts-down (master clk cycles) to 1, triggers the ramp se quence and updates the fine scale factor. the counter will then stop at a count of zero. if the counter is initially loaded with 0, then the scale hold-off counter is bypassed and will not trigger any succeeding events. there are three ways to provide the sync pulse that loads the hold-off counter that ultimately triggers the ramp: 1. serial input sync. this method is selected when ?erial time slot sync enable? 0xn16:2, is set to logic 1 and appropriate serial word input bits are set as described in figure 17 (AD6623 data format and bit definition chart). this allows a channel? fine scale hold-off counter to be loaded and a power ramp sequence to be triggered by a data word without resorting to hardware or software generated sync pulses. this sync signal is routed to the or gate following the time slot sync multi plexer shown in the sync control block diagram, figure 37. 2. hardware sync. sync pins 0, 1, 2, and 3 provide a means to load the fine scale hold-off counter using the channel? ?ime slot sync?multiplexer. the multiplexer allows selection of the desired hard or ?in?sync signal using two software controlled select lines at register addresses 0xn0f:17 and 0xn0f:16. pin-sync is the most precise method of synchro- nization. this block shares 2 signals with the beam sync block. they are software beam sync and sync0. this means that whenever a sync0 or soft beam sync is sent to the beam sync block, the same signals are also sent to the time slot sync block. 3. software sync. this function allows the user to load start, hop, beam and fine scale holdoff counters via software commands through the AD6623 microport. sync signals generated in this manner are the least precise means of syn chronization. all software sync bits are located at address 5 of the external register (see table xxi external registers). the time slot soft-sync is derived from the shared beam sync soft sync. setting d6, ?eam? high will generate a soft sync signal that loads the fine scale hold-off counter as well as the beam sync phase hold-off counter. user must select which channel(s) will receive the soft sync signal(s) using bits d0 through d3 at external address 5 and select what type of sync signal(s) is to be generated (using bits d4, 5 and 6 at address 5). as an example, to generate a time slot soft sync for channel c, a user would set bits d2 and d6 high. d6 is the actual sync signal and d2 routes the sync signal only to channel c. special handling required for sync0 pin-sync proper routing of sync0 (a hardware sync pulse) for time slot sync may require bits in several registers to be set depending upon the number of active channels. these control bits are located in the internal ?ommon function?registers (address 0x001) and the internal ?hannel function?registers (address 0xn00, 0xn03, 0xn05, 0xn0f). address 0x001 contains 8 bits that will mask the distribution of pin-sync pulses from sync0 to all channels and enable which sync multiplexers (start, hop, and beam) receive sync0 pulses. furthermore, the msb at 0x001 is a ?irst sync only?flag that, when high, allows only one sync0 pulse to be routed to the selected sync block(s). following this, all 8-bits of register 0x001 are cleared to completely mask off subsequent pulses.
rev. a AD6623 ?4 sync pulses from sync1, 2, and 3 pins are not masked in any fash- ion and directly connect to all sync multiplexers of all channels. the sync control block diagram, figure 37, in the synchroni zation section of this data sheet provides an overview of all sync signal routing for one channel. cascaded integrator comb (cic) interpolating filters the i and q outputs of the rcf stage are interpolated by two cascaded integrator comb (cic) filters. the cic section is sepa rated into three discrete blocks: a fifth order filter (cic5), a second order resampling filter (rcic2), and a scaling block (cic scaling). the cic5 and rcic2 blocks each exhibit a gain that changes w ith respect to their rate change factors, l rcic2 , m rcic2 , and l cic5 . the product of these gains must be compensated for in a shared cic scaling block and can be done to within 6 db. the remaining compensation can come from the rcf (in the form of coefficient scaling) or the fine scaling unit. cic scaling the scale factor s cic is a programmable unsigned integer between 4 and 32. this is a combined scaler for the cic5 and rcic2 stages. the overall gain of the cic section is given by the equation below cic gain l l cic rcic s cic _ = 5 4 2 2 (10) cic5 the first cic filter stage, the cic5, is a fifth order interpolating cascaded integrator comb whose impulse response is completely defined by its interpolation factor, l cic5 . the value l cic5 ? can be independently programmed for each channel at location 0xn09. 2 ?cic m rcic 2 l rcic 2 l cic5 cic_scale rcic2 cic5 figure 28. cic5 while this control register is 8 bits wide, l cic5 should be confined to the range from 1 to 32 to avoid the possibility of internal overflow for full scale inputs. the output rate of this stage is given by the equation below. ffl cic cic cic 255 = (11) the transfer function of the cic5 is given by the following equations with respect to the cic5 output sample rate, f samp5 . cic z z z l cic 5 1 1 5 1 5 () = ? ? ? ? ? ? (12) the scic value can be independently programmed for each channel at control register 0xn06. s cic may be safely calculated according to equation (13) below to ensure the net gain through the cic stages. scic serves to frame which bits of the cic output are transferred to the nco stage. this results in controlling the data out of the cic stages in 6 db increments. for the best dynamic range, s cic should be set to the smallest value possible (lowest attenuation) without creating an overflow condition. this can be safely accomplished using the equation below. to ensure the cic output data is in range, equation 13 must always be met. the maximum total interpolation rate may be limited by the amount of scaling available. s ceil l l cic cic cic ? () + () () 4 25 22 log log (13) 058 ? s cic (14) this polynomial fraction can be completely reduced as follows demonstrating a finite impulse response with perfect phase linearity for all values of l cic5 . cic z z z e k k l j k l k l cic cic cic 5 0 1 5 1 2 1 1 5 5 5 5 () = ? ? ? ? ? ? = ? ? ? ? ? ? == (15) the frequency response of the cic5 can be expressed as follows. the initial 1/l cic5 factor normalizes for the increased rate, which is appropriate when the samples are destined for a dac with a zero order hold output. the maximum gain is l cic5 4 at baseband, but internal registers peak in response to various dynamic inputs. as long as l cic5 is confined to 32 or less, there is no possibility of overflow at any register. cic f l lf f f f cic cic cic cic 5 1 5 5 5 5 5 () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sin sin (16) the pass band droop of cic5 should be calculated using this equation and can be compensated for in the rcf stage. the gain should be calculated from the cic scaling section above. as an example, consider an input from the rcf whose bandwidth is 0.141 of the rcf output rate, centered at baseband. interpolation by a factor of five reveals five images, as shown below. ?50 ? ? db 01 2 ?30 ?10 ?0 ?0 ?0 ?0 ?0 10 ? 3 figure 29. unfiltered cic5 images the cic5 rejects each of the undesired images while passing the image at baseband. the images of a pure tone at channel center (dc) are nulled perfectly, but as the bandwidth increases the rejection is diminished. the lower band edge of the first image always has the least rejection. in this example, the cic5 is interpolating by a factor of five and the input signal has a bandw idth of 0.141 of the rcf output sample rate. the plot below shows ?10 dbc rejection of the lower band edge of the first image. all other image frequencies have better rejection.
rev. a AD6623 ?5 ?50 ? db 012 ?30 ?10 ?0 ?0 ?0 ?0 ?0 10 ? ? 3 figure 30. filtered cic5 images table xii lists maximum bandwidth that will be rejected to various levels for cic5 interpolation factors from 1 to 32. the example above corresponds to the listing in the ?10 db column and the l cic5 = 5 row. it is worth noting here that the rejection of the cic5 improves as the interpolation factor increases. table xii. max bandwidth of rejection for l cic5 values l cic5 ?10 db ?00 db ?0 db ?0 db ?0 db 1 full full full full full 2 0.101 0.127 0.160 0.203 0.256 3 0.126 0.159 0.198 0.246 0.307 4 0.136 0.170 0.211 0.262 0.325 5 0.136 0.175 0.217 0.269 0.333 6 0.143 0.178 0.220 0.282 0.337 7 0.144 0.179 0.222 0.275 0.340 8 0.145 0.180 0.224 0.276 0.341 9 0.146 0.181 0.224 0.277 0.342 10 0.146 0.182 0.225 0.278 0.343 11 0.147 0.182 0.226 0.278 0.344 12 0.147 0.182 0.226 0.279 0.344 13 0.147 0.183 0.226 0.279 0.345 14 0.147 0.183 0.226 0.279 0.345 15 0.148 0.183 0.227 0.280 0.345 16 0.148 0.183 0.227 0.280 0.345 17 0.148 0.183 0.227 0.280 0.346 18 0.148 0.183 0.227 0.280 0.346 19 0.148 0.183 0.227 0.280 0.346 20 0.148 0.184 0.227 0.280 0.346 21 0.148 0.184 0.227 0.280 0.346 22 0.148 0.184 0.227 0.280 0.346 23 0.148 0.184 0.227 0.280 0.346 24 0.148 0.184 0.227 0.280 0.346 25 0.148 0.184 0.227 0.281 0.346 26 0.148 0.184 0.227 0.281 0.346 27 0.148 0.184 0.227 0.281 0.346 28 0.148 0.184 0.227 0.281 0.346 29 0.148 0.184 0.227 0.281 0.346 30 0.148 0.184 0.227 0.281 0.346 31 0.148 0.184 0.227 0.281 0.346 32 0.148 0.184 0.228 0.281 0.346 the rcic2 resampling interpolation filter the rcic2 filter is a second order re-sampling cascaded inte- grator comb filter whose impulse response is defined by its rate-change factors, l rcic2 and m rcic2 . the r cic2 filter is imple- mented using a technique that does not require a faster clock than the output rate thus simplifying design and saving power while maintaining jitter-free operation. the rcic2 stage allows for noninteger relationships between the input data rate and the master clock. this allows easier implementation of systems that are either multimode or require a clock that is not a multiple of the input data rate. the overall effect is referred to as ?ate- change? a specific rate-change is accomplished by choosing appropriate interpolation and decimation values for equation (17) below. for example, if an interpolation ratio of 2.69 is needed, then set l rcic2 = 269 and m rcic2 = 100. permissible values of l rcic2 and m rcic2 the two parameters that determine the rate-change of the rcic2 filter are: 1. the interpolation factor, l rcic2 , ranging from 1 to 4096 (12 bits) 2. the decimation factor, m rcic2 , ranging from 1 to 512 (9 bits) the range of l rcic2 is limited by l cic5 according to table x iii. table xiii. maximum permissible l rcic2 values chosen l cic5 value maximum allowed l rcic2 value 1 to 22 4095 23 3836 24 3236 25 2748 26 2349 27 2020 28 1746 29 1518 30 1325 31 1162 32 1024 m rcic 2 is restricted by equations (17) and (18) below. m l complex rcic rcic 2 2 1 + (17) where: l rcic 2 = interpolation of rcic2 complex = complex output mode (off = 0, on = 1), ()( )( ) 2461 5 2 2 + ++ ? ? ? ? ? ? tpp ape complex ceil l l m cic rcic rcic (18) where: tpp = taps per phase (of ram coefficient filter) ape = allpass phase equalizer (off = 0, on = 1) complex = complex output mode (off = 0, on = 1) ceil = when a value within the parenthesis is not an integer, then round-up to the next integer (e.g., 9.001 = 10) l cic5 = interpolation rate of cic5 l rcic2 = interpolation of rcic2 m rcic2 = decimation of rcic2
rev. a AD6623 ?6 resampling is implemented by apparently increasing the input sample rate by the factor l, using zero stuffing for the new data samples. following the resampler is a second order cascaded integrator comb filter. filter characteristics are determined only by the fractional rate change (l/m). the filter can produce output signals at the full clk rate of the AD6623. the output rate of this stage is given by the equation below. f l m f out rcic rcic rcic = 2 2 2 (19) both l rcic 2 and m rcic 2 are unsigned integers. the interpolation rate ( l rcic 2 ) may be from 1 to 4096 and the decimation ( m rcic 2 ) may be between 1 and 512. the stage can be bypassed by setting the l and m to 1. the transfer function of the rcic2 is given by the following equations with respect to the rcic2 output sample rate, f out . rcic z z z l rcic 2 1 1 2 1 2 () = ? ? ? ? ? ? (20) frequency response of rcic2 the frequency response of the rcic2 can be expressed as follows. the maximum gain is l rcic2 at baseband. the initial m rcic2 /l rcic2 factor normalizes for the increased rate, which is appropriate when the samples are destined for a dac with a zero order hold output. rcic f m l lf f f f rcic rcic rcic out out 2 2 2 2 2 () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sin sin (21) the pass-band droop of cic5 should be calculated using this equation and can be compensated for in the rcf stage. the gain should be calculated from the cic scaling section above. programming guidelines for AD6623 cic filters the values m rcic2 ?, l rcic2 ? can be independently pro- grammed for each channel at locations 0xn07, 0xn08. while these control registers are nine bits and 12 bits wide respec- tively, m rcic2 ? and l rcic2 ? should be confined to the ranges shown by table xiii according to the interpolation factor of the cic5. exceeding the recommended guidelines may result in overflow for input sequences at or near full scale. while rela- tively large ratios of l rcic2 /m rcic2 allow for the larger overall interpolations with minimal power consumption, l rcic2 /m rcic2 should be minimized to achieve the best overall image rejection. as an example, consider an input from the cic5 whose bandwidth is 0.0033 of the cic5 rate, centered at baseband. interpolation by a factor of five reveals five images, as shown below. ?50 ? ? db 01 2 ?30 ?10 ?0 ?0 ?0 ?0 ?0 10 ? 3 figure 31. unfiltered rcic2 images the rcic2 rejects each of the undesired images while passing the image at baseband. the images of a pure tone at channel center (dc) are nulled perfectly, but as the bandwidth increases the rejection is diminished. the lower band edge of the first image always has the least rejection. in this example, the rcic2 is interpolating by a factor of five and the input signal has a bandwidth of 0.0033 of the cic5 output sample rate. figure 32 shows ?10 dbc rejection of the lower band edge of the first image. all other image frequencies have better rejection. 10 db ?0 ?0 ? 3 ? ? 0 1 2 ?0 ?0 ?0 ?10 ?30 ?50 figure 32. filtered rcic2 images table xiv lists maximum bandwidth that will be rejected to various levels for cic2 interpolation factors from 1 to 32. the example above corresponds to the listing in the ?10 db column and the l rcic2 = 5 row. the rejection of the cic2 improves as the interpolation factor increases.
rev. a AD6623 ?7 in the complex mode, the nco serves as a quadrature local oscil lator running at f clk /2 capable of producing any frequency step between ? clk /4 and +f clk /4 with a resolution of f clk /2 33 (0.0121 hz for f clk = 104 mhz). in the real mode, the nco serves as a quadrature local oscillator running at f clk capable of producing any frequency step between ? clk /2 and +f clk /2 with a resolution of f clk /2 32 (0.0242 hz for f clk = 104 mhz). the quadrature portion of the output is discarded. negative frequencies are distinguished from positive frequencies solely by spectral inversion. the digital if is calcu lated using the equation: ff nco frequency if nco = _ 2 32 (22) where: nco_frequency is the decimal equivalent of the 32-bit binary value written to 0xn02, f if is the desired intermediate frequency (in hz), and f nco is f clk /2 (in hz) for complex outputs and f clk (in hz) for real outputs. phase dither the AD6623 provides a phase dither option for improving the spurious performance of the nco. phase dither is enabled by writing a ??to bit 3 of channel register 0xn01. when phase dither is enabled, spurs due to phase truncation in the nco are randomized. the choice of whether phase dither is used in a system will ultimately be decided by the system goals and the choice of if frequency. the 18 most significant bits of the phase accumulator are used by the angle to cartesian conversion. if the nco frequency has all zeroes below the 18 th bit, then phase dither has no effect. if the fraction below the 18 th bit is near a 1/2 or 1/3 of the 18 th bit, then spurs will accumulate separated from the if by 1/2 or 1/3 of the clk frequency. the smaller the denominator of this residual fraction, the larger the spurs due to phase truncation will be. if the phase truncation spurs are unacceptably high for a given frequency, then the phase dither can reduce these at the penalty of a slight elevation in total error energy. if the phase truncation spurs are small, then phase dither will not be effective in reducing them further, but a slight elevation in total error energy will occur. amplitude dither amplitude dither can also be used to improve spurious performance of the nco. amplitude dither is enabled by writing a ??to bit 4 of channel register at 0xn01. when enabled, amplitude dither can reduce spurs due to truncation at the input to the qam. if the entire frequency word is close to a fraction that has a small 32 32 q d pn gen. nco frequency w ord 16 phase offset 16 32 32 q d angle to cartesian conversion pn gen. i data from cic5 q data from cic5 i q i, q clk on off on off 32 32 microprocessor interface figure 33. numerically controlled oscillator and qam mixer table xiv. maximum bandwidth of rejection for l rcic2 values l rcic2 ?10 db ?00 db ?0 db ?0 db ?0 db 1 full full full full full 2 0.0023 0.0040 0.0072 0.0127 0.0226 3 0.0029 0.0052 0.0093 0.0165 0.0292 4 0.0032 0.0057 0.0101 0.0179 0.0316 5 0.0033 0.0059 0.0105 0.0186 0.0328 6 0.0034 0.0060 0.0107 0.0189 0.0334 7 0.0034 0.0061 0.0108 0.0192 0.0338 8 0.0035 0.0062 0.0109 0.0193 0.0341 9 0.0035 0.0062 0.0110 0.0194 0.0343 10 0.0035 0.0062 0.0110 0.0195 0.0344 11 0.0035 0.0062 0.0110 0.0195 0.0345 12 0.0035 0.0062 0.0111 0.0196 0.0346 13 0.0035 0.0062 0.0111 0.0196 0.0346 14 0.0035 0.0063 0.0111 0.0196 0.0346 15 0.0035 0.0063 0.0111 0.0197 0.0347 16 0.0035 0.0063 0.0111 0.0197 0.0347 17 0.0035 0.0063 0.0111 0.0197 0.0347 18 0.0035 0.0063 0.0111 0.0197 0.0348 19 0.0035 0.0063 0.0111 0.0197 0.0348 20 0.0035 0.0063 0.0111 0.0197 0.0348 21 0.0035 0.0063 0.0111 0.0197 0.0348 22 0.0035 0.0063 0.0111 0.0197 0.0348 23 0.0035 0.0063 0.0111 0.0197 0.0348 24 0.0035 0.0063 0.0112 0.0197 0.0348 25 0.0035 0.0063 0.0112 0.0198 0.0348 26 0.0035 0.0063 0.0112 0.0198 0.0349 27 0.0035 0.0063 0.0112 0.0198 0.0349 28 0.0035 0.0063 0.0112 0.0198 0.0349 29 0.0035 0.0063 0.0112 0.0198 0.0349 30 0.0035 0.0063 0.0112 0.0198 0.0349 31 0.0035 0.0063 0.0112 0.0198 0.0349 32 0.0035 0.0063 0.0112 0.0198 0.0349 numerically controlled oscillator/tuner (nco) each channel has a fully independent tuner. the tuner accepts data from the cic filter, tunes it to a digital intermediate frequency (if), and passes the result to a shared summation block. the tuner consists of a 32-bit quadrature nco and a quadra ture amplitude mixer (qam). the nco serves as a local oscillator and the qam translates the interpolated channel data from baseband to the nco frequency. the worst case spurious signal from the nco is better than ?00 dbc for all output frequencies. the tuner can produce real or complex outputs as requested by the shared summation block.
rev. a AD6623 ?8 denominator, the spurs due to amplitude truncation will be large and amplitude dither will spread these spurs effectively. amplitude dither also will increase the total error energy by approximately 3 db. for this reason amplitude dither should be used judiciously. phase offset the phase offset (channel register 0xn04) adds an offset to the phase accumulator of the nco. this is a 16-bit register that is interpreted as a 16-bit unsigned integer. phase offset ranges from 0 to nearly 2 radians with a resolution of /32768 radians. this register allows multiple ncos to be synchronized to produce sine waves with a known phase relationship. nco frequency update and phase offset update hold-off counters the update of both the nco frequency and phase offset can be synchronized with internal hold-off counters. both of these counters are 16-bit unsigned integers and are clocked at the master clk rate. these hold-off counters used in conjunc tion with the fre- quency or phase offset registers, allow beam forming and frequency hopping. see the synchronization section of the d ata sheet for additional details. the nco phase can also be cleared on sync (set to 0x0000) by setting bit 2 of channel register 0xn01 high. nco control scale the output of the nco can be scaled in four steps of 6 db each via channel register 0xn01, bits 1?. table xv show a breakdown of the nco control scale. the nco always has loss to accommodate the possibility that both the i and q inputs may reach full-scale simultaneously, resulting in a 3 db input magnitude. table xv. nco control scale 0xn01 bit 1 0xn01 bit 0 nco output level 00 ? db (no attenuation) 01 ?2 db attenuation 10 ?8 db attenuation 11 ?4 db attenuation summation block the summation block of the AD6623 serves to combine the outputs of each channel to create a composite multicarrier signal. the four channels are summed together and the result is then added with the 18-bit wideband input bus (in[17:0]). the final summation is then driven on the 18-bit wideband output bus (out[17:0]) on the rising edge of the high speed clock. if the oen input is low then this output bus is three-stated. if the oen input is high then this bus will be driven by the summed data. the oen is active high to allow the w ideband output bus to be connected to other busses without using extra logic. most other busses (like 374 type registers) require a low output enable, which is opposite of the AD6623 oen, thus eliminating extra circuitry. dual 18-bit output configuration the wideband parallel input in[17:0] is defined as bidirec tional, to support dual parallel outputs. each parallel output produces the sum of two of the four internal tsps and AD6623 that can drive two dacs. channels are added in pairs (a + b), (c + d) as shown in figure 34. channels a + b out [17:0] i n/ out [17:0] channels c + d 14-bit dac 14-bit dac AD6623 figure 34. AD6623 driving two dacs output data format the wideband output bus may be interpreted as a two? comple- ment number or as an offset binary number as defined by bit 1 of the summation mode control register at address 0x000. when this bit is high, then the wideband output is in two? complement mode and when it is low it is configured for offset binary output data. offset binary data format is used w hen d riving an offset binary dac or test equipment, etc., that can accept offset binary. the two? complement mode should be used in the following circumstances: ? when driving a dac that accepts two? complement data ? when driving another AD6623 in cascade mode ? when driving test equipment, fifo memory, etc. that can accept two? complement data format output clip detection the msb (bit 17) of the wideband output bus is typically used as a guard bit for the purpose of clipping the wideband output bus when bit 0 of the summation mode control register at address 0x000 is high. if clip detection is enabled then bit 17 of the output bus is not used as a data bit. instead, bit 16 will become the msb and is connected to the msb of the dac. configuring the dac in this manner gives the summation block a gain of 0 db. when clip detection is not enabled and bit 17 is used as a data bit then the summation block will have a gain of ?.02 db. there are two data output modes. the first is offset binary. this mode is used only when driving offset binary dacs. two? comple- ment m ode may be used in one of two circumstances. the first is when driving a dac that accepts two? complement data. the second is when driving another AD6623 in cascade mode. when clipping is enabled, the two? complement mode output bus will clip to 0x2ffff for output signals more positive than the output can express and it will clip to 0x3000 for signals more nega tive than the output can express. in offset binary mode the output bus will clip to 0x3ffff for output signals more positive than the output can express and it will clip to 0x2000 for signals mor e negative than the output can express. cascading multiple AD6623s the wideband input is always interpreted as an 18-bit two? complement number and is typically connected to the wideband output bus of another AD6623 in order to send more than four carriers to a single dac. the output bus of the preceding AD6623 should be configured in two? complement mode and clip detection disabled. the 18-bit resolution insures that the noise and spur performance of the wideband data stream does not become the limiting factor as large numbers of carriers are summed. there is a two-clock cycle latency from the wideband input bus to the wideband output bus. this latency may be calibrated out of the system by use of the start hold-off counter. the preceding AD6623 in a cascaded chain can be started two clk cycles before the following AD6623 is started and the data from eac h AD6623 will arrive at the dac on the same clock cycle. in systems where the individual signals are not correlated, this is usually not neces sary.
rev. a AD6623 ?9 selection of real and complex output data types the AD6623 is capable of outputting both real and complex data. when in real mode the qin input is tied low signaling that all inputs on the wideband input bus are real and that all outputs on the wideband output bus are real. the wideband input bus will be pulled low and no data will be added to the composite signal if this port is unused (not connected). if complex data is desired there are two ways this can be obtained. the first method is to simply set the qin input of the AD6623 high and to set the wideband input bus low. this allows the AD6623 to output complex data on the wideband output bus. the i data samples would be identified when qout is low and the q data samples would be identified when qout is high. the second method of obtaining complex data is to provide a qin signal that toggles on every rising edge of the clk. this could be obtained by connecting the qout of another AD6623 to qin as shown in figure 35. in a cascaded system the qin of the first AD6623 in the chain would typically be tied high and the qout of the first AD6623 would be connected to the qin of the following part. all AD6623s will synchronize themselves to the qin input so that the proper samples are always paired and the wideband output bus represents valid complex data samples. table xvi shows different parallel input and output data bus formats as a function of qin and qout. table xvi. valid output bus data modes wideband input output data type qin in[17:0] out[17:0], qout low real real high zero complex pulsed complex complex 14-bit dac out [16:3] in [17:0] out [17:0] q in q out in [17:0] q in AD6623 AD6623 logic1 logic0 figure 35. cascade operation of two AD6623s synchronization three types of synchronization can be achieved with the AD6623. these are start, hop, and beam. each is described in detail below. the synchronization is accomplished with the use of a shadow register and a hold-off counter. see figure 36 for a simplistic schematic of the nco shadow register and nco frequency hold-off counter to understand basic operation. enabling the clock (AD6623 clk) for the hold-off counter can occur with either a soft_sync (via the microport), or a pin sync. the functions that include shadow registers to allow synchronization include: 1. start 2. hop (nco frequency) 3. beam (nco phase offset) hold-off counters and shadow registers hold-off counters are used with the five synchronized AD6623 functions: ? start of channel(s) ? rcf fine scale output level update ? power ramping of time slot transmissions ? frequency hopping ? phase shifting for beam controlstart these are 16-bit counters that are preloaded with a programmable value upon receipt of a synchronizing pulse. the counter then counts down to zero and stops. the counters are re-triggerable during countdown. if the counter is re-triggered, it re-loads its count value and starts again and may preclude the triggering of the event as intended. when the count reaches one, a trigger signal is emitted which causes the desired event (start, ramp, hop, beam, scale) to commence. the counters are clocked with the AD6623 clk that determines the time resolution of the each count. with a 104 mhz clk, the resolu tion is approximately 10 ns and the delay range is from approximately 20 ns to 0.6 ms. if a hold-off counter is loaded with 0, it will not respond to synchronizing pulses and the event will not be triggered by the hold-off counter. the AD6623 can ?rigger?all of the aforementioned events except ramping without a soft-sync, pin-sync, or data-sync. this is through the use of the sleep bit for each channel at external address 5. whenever a channel is brought out of sleep mode (sleep bit = low) an automatic pulse updates all active and shadow registers. this feature allows a channel to be reprogrammed w hile it is sleeping and then activated with immediate implementation of the changes. shadow register are provided for three functions, frequency hop, fine scale, and phase offset. a shadow register precedes an active register. it holds the next number to be used by the active register whenever that function? hold-off counter causes the active register to be updated with the new value. active registers are also updated with the contents of a shadow register any time the channel is brought out of the sleep mode. a shadow register is updated during normal programming of the registers through the microport. active registers for frequency, fine scale and phase offset words can only receive their update data from a shadow register. when software reads-back a channel? programmed values, it is reading back the shadow registers of the fine scale and phase offset functions but reads the active frequency register as shown in figure 36. 32 nco shadow register q d q d nco register nco phase a ccumulator 32 32 ena 16 q d q d q clr set sleep hop holdoff hop sync start holdoff holdoff counter start counter reset pin clk start sync 16 16 16 clr microprocessor interface d c = 1 c = 0 pl ena d c = 1 c = 0 pl ena figure 36. nco shadow register and hold-off counter
rev. a AD6623 ?0 start refers to the start-up of an individual channel, chip, or multiple chips. if a channel is not used, it should be put in the sleep mode to reduce power dissipation. following a hard reset (low pulse on the AD6623 reset pin), all channels are placed in the sleep mode. start with no sync if no synchronization is needed to start multiple channels or multiple AD6623s, the following method should be used to initialize the device. 1. to program a channel, it must first be set to the program mode (bit high) and sleep mode (bit high) (ext address 4). the program mode allows programming of data memory and coefficient memory (all other registers are programmable whether in program mode or not). since no synchronization is used, all sync bits are set low (external address 5). all appro- priate control and memory registers (filter) are then loaded. the start update hold-off counter (0xn00) should be set to 0. 2. set the appropriate program and sleep bits low (ext address 4). this enables the channel. the channel must have program and sleep mode low to activate a channel. start with softsync the AD6623 includes the ability to synchronize channels or chips under microprocessor control. one action to synchronize is the start of channels or chips. the start update hold-off counter (0xn00) in conjunction with the start bit and sync bit (ext address 5) allow this synchronization. basically the start update hold-off counter delays the start of a channel(s) by its value (number of AD6623 clks). the following method is used to syn- chronize the start of multiple channels via microprocessor control. 1. set the appropriate channels to sleep mode (a hard reset to the AD6623 reset pin brings all four channels up in s leep m ode). 2. write the start update hold-off counter(s) (0xn00) to the appropriate value (greater than 1 and less than 2 16 ?). if the chip(s) is not initialized, all other registers should be loaded at this step. 3. write the start bit and the syncx(s) bit high (ext address 5). 4. this starts the start update hold-off counter countin g down. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the sleep bit of the appropriate channel(s) is set low to activate the channel(s). start with pin sync four hardware sync pins are available on the AD6623 to pro- vide the most accurate synchronization, especially between multiple AD6623s. synchronization of start with an external signal is accomplished with the following method. 1. set the appropriate channels to sleep mode (a hard reset to the AD6623 reset pin brings all four channels up in sleep mode). 2. write the start update hold-off counter(s) (0xn00) to the appropriate value (greater than 1 and less than 2 16 ?). if the chip(s) is not initialized, all other registers should be loaded at this step. 3. set the start on pin sync bit and the appropriate sync pin enable high (0xn01). 4. when the sync pin is sampled high by the AD6623 clk this enables the count down of the start update hold-off counter. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the sleep bit of the appropriate channel(s) is set low to activate the channel(s). hop a jump from one nco frequency to a new nco frequency. this change in frequency can be synchronized via microprocessor control or an external sync signal as described below. to set the nco frequency without synchronization the following method should be used. set frequency no hop 1. set the nco frequency hold-off counter to 0. 2. load the appropriate nco frequency. the new frequency will be immediately loaded to the nco. hop with softsync the AD6623 includes the ability to synchronize a change in nco frequency of multiple channels or chips under microprocessor control. the nco frequency hold-off counter (0xn03) in con junction with the hop bit and the sync bit (ext address 5) allow this synchronization. basically the nco frequency hold-off counter delays the new frequency from being loaded into the nco by its value (number of AD6623 clks). the following method is used to synchronize a hop in frequency of multiple channels via m icroprocessor control. 1. write the nco frequency hold-off (0xn03) counter to the appropriate value (> 1 and < 2 16 ?). 2. write the nco frequency register(s) to the new desired frequency. 3. write the hop bit and the sync(s) bit high (ext address 5). 4. this starts the nco frequency hold-off counter counting down. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the new frequency is loaded into the nco. hop with pin sync four hardware sync pins are available on the AD6623 to pro- vide the most accurate synchronization, especially between multiple AD6623s. synchronization of hopping to a new nco frequency with an external signal is accomplished with the fol- lowing method. 1. write the nco frequency hold-off counter(s) (0xn03) to the appropriate value (greater than 1 and less than 2 16 ?). 2. write the nco frequency register(s) to the new desired frequency. 3. set the hop on pin sync bit and the appropriate sync pin enable high (0xn01). 4. when the sync pin is sampled high by the AD6623 clk this enables the count down of the nco frequency hold-off counter. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the new frequency is loaded into the nco.
rev. a AD6623 ?1 beam a change in phase for a particular channel and can be synchronized with respect to other channels or AD6623s. this change in phase can be synchronized via microprocessor control or an external sync signal. to set the amplitude without synchronization the following method should be used. set phase no beam 1. set the nco phase offset update hold-off counter ( 0xn05) to 0. 2. load the appropriate nco phase offset (0xn04). the nco phase offset will be immediately loaded. beam with softsync the AD6623 includes the ability to synchronize a change in nco phase of multiple channels or chips under microprocessor control. the nco phase offset update hold-off counter in conjunction with the beam bit and the sync bit (ext address 5) allow this synchronization. basically the nco phase offset update hold-off counter delays the new phase from being loaded into the nco/rcf by its value (number of AD6623 clks). the following method is used to synchronize a beam in phase of multiple channels via mi croprocessor control. 1. write the nco phase offset update hold-off counter (0xn05) to the appropriate value (greater than 1 and less then 2 16 ?). 2. write the nco phase offset register(s) to the new desired phase and amplitude. 3. write the beam bit and the sync(s) bit high (ext address 5). 4. this starts the nco phase offset update hold-off counter counting down. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the new phase is loaded into the nco. beam with pin sync four hardware sync pins are available on the AD6623 to pro vide the most accurate synchronization, especially between multiple AD6623s. synchronization of beaming to a new nco phase offset with an external signal is accomplished using the follow ing method. 1. write the nco phase offset hold-off (0xn05) counter(s) to the appropriate value (greater than 1 and less than 2 16 ?). 2. write the nco phase offset register(s) to the new desired phase and amplitude. 3. set the beam on pin sync bit and the appropriate sync pin enable high (0xn01). 4. when the sync pin is sampled high by the AD6623 clk this enables the count down of the nco phase offset hold-off counter. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the new phase is loaded into the nco registers. time slot (ramp) this enables power ramping and allows input data format changes during the ?uiet?period after ramp-down. it must be synchronized using the microport (soft sync), input data or a hardware sync pin. a time slot normally takes the form of: ramp-down to minimum power, ?est?period and ramp-up to maximum output power. see the ?cf power ramping section of this data sheet for related information. the prog mode bits located at external address 4:7-4, referred to below, must be set high whenever rmem (ramp memory), cmem (coefficient memory) or dmem (data memory) are to be programmed. however, when programming is completed, the prog bit for the channel(s) must be returned low for proper channel functioning. set output power, no ramp the steps below assume that the user has established a data flow from input to output of the AD6623. 1. place the channel(s) in sleep mode (external address 4:3-0, write bit(s) high). 2. set bit 0 of internal address 0xn16 (the channel? ramp enable bit) to logic 0. this defeats the ramp function. 3. set the fine scaling and coarse scaling control register values associated with the rcf (0xn0d:7-6 and 0xn0e:15-2), cic (0xn06:4-0), nco (0xn01:1-0) and summation stages to the desired levels according to the scaling section of this data sheet. 4. finally, re-establish an output data flow to a dac by bringing the appropriate sleep bits low and verify desired signal ampli- tude. note: a start sync pulse is automatically generated when the channel is brought out of sleep mode. the start pulse loads the updated control register data to the appropriate active counters and shadow registers. time slot (ramp) with softsync time slot or ramping functions for each channel can be engaged with software synchronizing words received through the micro- port. the rcf fine scale hold-off counter in conjunction with the beam bit * (which is the sync signal) and synca, b, c, and/or d (the channel to be sync?d) in external register address 5 allow this synchronization. the rcf fine scale hold-off counter delays the beginning of the time slot function as well as updating the fine scale amplitude value (if applicable). the amount of time delay is set by the value (number of AD6623 clk periods) written to the register at 0xn0f:15-0. since the time slot event is of short duration, the user should consider a digital scope set for normal or one-shot triggering to capture the event and verify functionality. the following steps are used to synchronize a time slot or ramp event with a software word received through the microport; they assume that the user has established a data flow from input to output of the AD6623. 1. place the channel(s) in sleep mode (external address 4:3-0, write bit(s) high) and in the prog mode (external address 4:7-4, write the bit(s) high). 2. write the fine scale hold-off counter (0xn0f:15-0) to the appropriate value (>1 and <2 16 ?). 3. set the ramp enable bit (0xn16:0) high. 4. load rmem (ramp memory) with up to 64 coefficients (0xn40-17f) with the desired values ranging from 0 to 2 14 ? that represent the ?hape?of the ramp transition. where 0 is zero gain and 2 14 ? is unity gain. 5. load the channel? ramp length minus 1, up to 63 at 0xn17 6. load the channel? ramp rest time minus 1, up to 31, at 0xn19. 7. re-establish an output data flow to the dac by bringing the channel(s) sleep bits low and prog bits low. 8. write the beam bit * high and desired sync(a, b, c, and/or d) bit(s) high at ext. address 5. return beam bit to logic 0. * the ?eam?soft sync signal is also routed to the time slot function. this is a ?hared?bit and it provides soft sync pulses to both the phase hold-off and fine scale hold-off counters simultaneously.
rev. a AD6623 ?2 9. this starts the fine scale hold-off counter counting down. the counter is clocked with the AD6623 clk signal. when it reaches a count of one, the ramp will commence from the last coefficient until it reaches the first coefficient of the specified ramp length. if a rest has been programmed, rest will commence for the programmed length and then the ramp will begin again at the first coefficient and ending at the last coefficient in the rmem (ramp memory). time slot with pin sync the procedure for using the hardware synchronizing pins ( sync0, 1, 2, and 3) to engage the time slot function is very similar to the soft sync. so for this case, only the differences between the two methods will be noted. it will be helpful to examine the hardware and software sync control block dia gram, figure 37, in order to visualize the process. hardware sync pins, (sync0, 1, 2, and 3), are all capable of loading the fine scale hold-off counters that trigger the ramp function of any channel. the sync pin labels do not signify attachment to specific channels, but conversely, each sync pin is routed directly or indirectly to every channel. the task that the user faces is to see that the sync signal is properly routed and selected. the time slot sync multiplexer seen in figure 37 is used to select a hardware pin sync signal. sync1, 2, and 3 are directly routed to the multiplexer, whereas sync0 is routed through two and gates before it reaches the multiplexer. the and gates duplicate the ad6622 single sync pin function to allow pin compatibility. * sync0 is routed in parallel to both the beam and time slot multiplexers and it is a ?hared?signal after is has been enabled at 0x001:6. to use sync1, 2, or 3, simply set the select ?ines?according to the channel register address (0xn0f:16-17) for the desired sync signal. attach a sync signal source to the package pin. when it is time to sync, assert a logic high (minimum 1 clk period +2 ns duration) and return to logic 0. this loads the fine scale hold-off counter and a countdown commences. holding a logic high at the chosen sync input pin longer than needed will result in additional delay as the scale hold-off counter is continually loaded with the same beginning count. from the block diagram, figure 37, it can be seen (note the or gates at the output of each multiplexer) that a software sync can also be used in conjunction with a hardware sync without any modification to the hardware setup. sync0 is selected at the time slot multiplexer using the same select ?ines?at 0xn0f:16-17 as for sync 1, 2, and 3; however, two additional ?asking?registers must be dealt with to get sync0 routed to the time slot sync multiplexer. first, sync0 must be enabled to enter the desired channel(s) using common function register address 0x001:3-0 (logic high = selected). secondly, once the channel(s) is/are selected, then the beam * multiplexer must be selected as the destination fo r sync0 by setting 0x001:6 to logic high. once the pin sync signals have been connected, routed and selected, the procedure for triggering a time slot or ramp sequence is nearly identical as outlined for a soft sync except for step 8. the user should substitute the pin-sync procedure in place of the soft sync method. to fine scale holdoff counter to p hase holdoff counter to hop holdoff counter to st art holdoff counter software beam/time slot sync 0x001:6 software hop sync 0x001:5 software start sync 0x001:4 cha. a start sync mux select lines from control register cha. a hop sync mux select lines from control register cha. a phase or beam sync mux select lines from control register cha. a time slot sync select lines from control register 0x001:4 start sync sync0 sync1 sync2 sync3 0x100:17 0x100:16 0x001:5 hop sync sync0 sync1 sync2 sync3 0x103:17 0x103:16 0x001:6 beam sync sync0 sync1 sync2 sync3 0x105:17 0x105:16 sync0 sync1 sync2 sync3 0x10f:17 0x10f:16 channel a sync0 enable 0x001:0 channel b sync0 enable 0x001:1 channel c sync0 enable 0x001:2 channel d sync0 enable 0x001:3 to channel a multiplexers to channel b multiplexers to channel c multiplexers to channel d multiplexers hardware sync pins sync3 pin sync2 pin sync1 pin sync0 pin * sync 1, 2, and 3 r oute directly to each channel mux for every sync function * h ardware sync 0 is configured to match the sync function of the ad6622 for pin compatibility figure 37. block diagram of hardware and software sync control for one AD6623 sync channel
rev. a AD6623 ?3 jtag interface the AD6623 supports a subset of ieee standard 1149.1 specifica- tion. for additional details of the standard, please see ieee standard test access port and boundary-scan architecture , ieee-1149 publication from ieee. the AD6623 has five pins associated with the jtag interface. these pins are used to access the on-chip test access port and are listed in table xvii. table xvii. test access port pins name pin number description trst 100 test access port reset tck 101 test clock tms 106 test access port mode select tdi 108 test data input tdo 107 test data output note that tck and tdi are internally pulled down which is opposite of ieee standard 1149.1. these pins may be connected to external pull-up resistors, with the associated additional current draw through the pull-ups, or left unconnected. the AD6623 supports four op codes are shown in table xviii. these instructions set the mode of the jtag interface. table xviii. op codes instruction op code idcode 10 bypass 11 sample/preload 01 extest 00 the vendor identification code (table xix) can be accessed through the idcode instruction and has the following format. table xix. vendor identification code msb part manufacturer lsb version number id number mandatory 0000 0010 0111 1000 0000 000 1110 0101 1 a bsdl file for this device is available from analog devices, inc. contact analog devices for more information. scaling proper scaling of the wideband output is critical to maximize the spurious and noise performance of the AD6623. a relatively small overflow anywhere in the data path can cause the spurious free dynamic range to drop precipitously. scaling down the output levels also reduces dynamic range relative to an approximately constant noise floor. a well-balanced scaling plan at each point in the signal path will be rewarded with optimum performance. the scaling plan can be separated into two parts: multicarrier scaling and single-carrier scaling. multicarrier scaling an arbitrary number of AD6623s can be cascaded to create a composite digital if with many carriers. as the number of carriers increases, the peak to rms ratio of the composite digital if will increase as well. it is possible and beneficial to limit the peak to rms ratio through careful frequency planning and controlled phase offsets. nevertheless, in most cases with a large number of carriers, the worst-case peak is an unlikely event. the AD6623 immediately preceding the dac can be programmed to clip rather than wrap around (see the summation block de scription). for a large number of carriers, a rare but finite chance of clipping at the AD6623 wideband output will result in supe- rior dynamic range compared to lowering each carrier level until clipping is impossible. this will also be the case for most dacs. through analysis or experimentation, an optimal output level of individual carriers can be determined for any particular dac. single-carrier scaling once the optimal power level is determined for each carrier, one must determine the best way to achieve that level. the maximum snr can be achieved by maximizing the intermediate power level at each processing stage. this can be done by assuming the proper level at the output and working along the following path: summation, nco, cic, ramp, rcf, and finally, fine scaler unit. the summation block is intended to combine multiple carriers with each carrier at least 6 db below full scale. for this configuration, the AD6623 driving the dac should have clip detection enabled. out17 becomes a clip indicator that reports clipping in both polarities. if the dac requires offset binary outputs, then the internal offset binary conversion should be enabled as well. any preceding cascaded AD6623s should disable clip detection and offset binary conversion. the in17?n0 of the first AD6623 in the cascade should be grounded. see the summation block section for details. in this configuration, intermediate out17s will serve as guard bits that allow intermediate sums to exceed full scale. as long as the final output does not exceed 6 db over full scale, the clip detector will perform correctly. if a single carrier needs to exceed ? db full scale, hardwired scaling can be accomplished according to table xx. this is most useful when the AD6623 is processing a single wideband carrier such as umts or cdma 2000. table xx. hardwired scaling max. single connect to clip offset binary carrier level dac msb detect compensation ?2.04 db out17 n/a internal ?.02 db out16 internal 0 db out15 + only 0x08000 +6.02 db out14 + only 0x0c000 the nco/tuner is equipped with an output scaler that ranges from ?.02 db to ?4.08 db below full scale, in +6.02 db steps. see the nco/tuner section for details. the best snr will be achieved by maximizing the input level to the nco and using the largest possible nco attenuation. for example, to achieve an output level ?0 db below full scale, one should set the cic output level to ?.94 db below full scale and attenuate by ?8.06 db in the nco. the cic is equipped with an output scaler that ranges from 0 db to ?86.64 db below full scale in +6.02 db steps. this large attenua tion is necessary to compensate for the potentially large gains associ ated with cic interpolation. see the cic section for details. for example to achieve an output level of ?.94 db below full scale, with a cic5 interpolation of 27 (+114.51 db gain) and a cic2 interpolation of 3 (+9.54 db gain), one should set the cic_scale to 20 and the fine scale unit output level to ?.59 db below full scale.
rev. a AD6623 ?4 ? . . . ? 194 954 114 51 20 6 02 5 59 + = (23) the ramp unit when bypassed will have exactly 0 db of gain and can be ignored. when in use, the gain is dependant on what value is stored in the last valid rmem location. rmem words are 14 bits [0?), so when the value is positive full scale, the gain is about ?.0005 db; probably neglectable. the rcf coefficients should be normalized to positive full scale. this will yield the greatest dynamic range. the rcf is equipped with an output scaler that ranges from 0 db to ?8.06 db below full scale in +6.02 db steps. this attenuation can be used to par- tially compensate for filter gain in the rcf. for example, if the maximum gain of the rcf coefficients is +11.26 db, the rcf coarse scale should be set to 2 (+12.04 db). this yields an rcf output level and fine scale input level of ?.78 db 11 26 12 04 0 78 .. . = (24) the fine scale unit is left to turn a ?.78 db level into a ?.59 db microport interface the microport interface is the communications port between the AD6623 and the host controller. there are two modes of bus operation: intel nonmultiplexed mode (inm), and motorola nonmultiplexed mode (mnm) that is set by hard-wiring the mode pin to either ground or supply. the mode is selected based on the use of the microport control lines (ds or rd, dtack or rdy, rw, or wr) and the capabilities of the host processor. see the timing diagrams for details on the operation of both modes. the external memory map provides data and address registers to read and write the extensive control registers in the internal memory map. the control registers access global chip functions and multiple control functions for each independent channel. microport control all accesses to the internal registers and memory of the AD6623 are accomplished indirectly through the use of the microprocessor port external registers shown in table xxi. accesses to the exter- nal registers are accomplished through the 3 bit address bus (a[2:0]) and the 8-bit data bus (d[7:0]) of the AD6623 (microport). external address [3:0] provides access to data read from or written to the internal memory (up to 32 bits). external address [0] is the least significant byte and external address [3] is the most signifi- cant byte. external address [4] controls the sleep mode of each level. this requires a gain of ?.81 db, which corresponds to a 14-bit [0?] scale value of 1264h. all subsequent rescalings during chip operation should be relative to this maximum. ? . ? 559 078 481 = (25) floor h 10 2 1264 481 20 13 ? ? ? ? ? ? ? = (26) finally, as described in the rcf section, there may be a worst-case peak of a phase that is larger than the channel center gain. in the preceding example, if the worst case to channel center ratio is larger than 4.59 db (potentially overflowing the rcf), then the rcf_ coarse_scale should be reduced by one and the cic_scale should be increased by one. in the preceding example, if the worst case to channel center ratio is larger than 5.59 db (potentially over flowing the rcf and cic), then the rcf_coarse_scale should be reduced by one and the nco_output_scale should be increased by one. channel. external address [5] controls the sync status of each channel. external address [7:6] determines the internal address selected and whether this address is incremented after subsequent reads and/or writes to the internal registers. external memory map the external memory map is used to gain access to the internal memory map described below. external address [7:6] sets the internal address to which subsequent reads or writes will be per- formed. the top two bits of external address [7] allow the user to set the address to auto increment after reads, writes, or both. all internal data words have widths that are less than or equal to 32 bits. accesses to external address [0] also triggers access to the AD6623? internal memory map. thus during writes to the internal registers, external address [0] must be written last to insure all data is transferred. reads are the opposite in that external address [0] must be the first data register read (after setting the appropriate internal address) to initiate an internal access. external address [5:4] reads and writes are transferred immediately to internal control registers. external address [4] is the sleep register. the sleep bits can be set collectively by the address. the sleep bits can be cleared by operation of start syncs as shown in table xxi. ram coefficient filter rcf coarse scaling rcf fine scaling multiplier channel summation stage nco scaling cic scaling rcf power ramping multiplier cic interpolation filters serial base- b and data in 1 of 4 channels coefficient scaling will affect numer- ical magnitude of data 0db to ?8db a ttenuation range with 2-bit (6db/step) resolution multiplier range is from 0 to 2 with 16-bit resolution ramp multiplier range 0 to 1 with 14-bit resolution and up to 128 ramp/down steps 18-bit digital if out ?2db to +6db hard-wired output bit scaling is an option ?db to ?4db a ttenuation range with 2-bit (6db/step) resolution 0db to ?86db, 6db steps with 5-bit resolution figure 38. AD6623 stage-by-stage summary of available scaling and power ramping functions
rev. a AD6623 ?5 table xxi. external registers external data external address d7 d6 d5 d4 d3 d2 d1 d0 7:uar wrinc rdinc iaii iaio ia9 ia8 6:lar ia7 ia6 ia5 ia4 ia3 ia2 ia1 ia0 5:softsync beam hop start sync d sync c sync b sync a 4:sleep prog d prog c prog b prog a sleep d sleep c sleep b sleep a 3:byte3 id31 id30 id29 id28 id27 id26 id25 id24 2:byte2 id23 id22 id21 id20 id19 id18 id17 id16 1:byte1 id15 id14 id13 id12 id11 id10 id9 id8 0:byte0 id7 id6 id5 id4 id3 id2 id1 id0 external address [5] is the sync register. these bits are write only. there are three types of syncs: start, hop, and beam. each of these can be sent to any or all of the four channels. for example, a write of x0010100 would issue a start sync to channel c only. a write of x1101111 would issue a beam sync and a hop sync to all channels. the internal address bus is 12 bits wide and the internal data bus is 32 bits wide. external address 7 is the uar (upper address register) and stores the upper four bits of the address space in uar[3:0]. uar[7:6] define the auto-increment feature. if bit 6 is high, the internal address is incremented after an internal read. if bit 7 is high, the internal address is incremented after an internal write. if both bits are high, the internal address in incremented after either a write or a read. this feature is designed for sequential access to internal locations. external address 6 is the lar (lower address register) and stores the lower 8 bits of the internal address. external addresses 3 through 0 store the 32 bits of the internal data. all internal accesses are two clock cycles long. writing to an internal location with a data width of 16 bits is achieved by first writing the upper four bits of the address to bits 3 through 0 of the uar (bits 7 and 6 of the uar are written to determine whether or not the auto increment feature is enabled). the lar is then written with the lower eight bits of the internal address (it doesn? matter if the lar is written before the uar as long as both are written before the internal access). since the data width of the internal address is 16 bits, only data register 1 and d ata r egister 0 are needed. data register 1 must be written first because the write to data register 0 triggers the internal access. data register 0 must always be the last register written to initiate the internal write. reading from the microport is accomplished in a similar manner. the internal address is first written. a read from data register 0 activates the internal read, thus register 0 must always be read first to initiate an internal read. this provides the 8 lsbs of the internal read through the microport (d[7:0]). additional bytes are then read by changing the external address (a[2:0]) and performing additional reads. if data register 3 (or any other) is read before data register 0, incorrect data will be read. data register 0 must be read first in order to transfer data from the core memory to the e xternal memory locations. once the data register is read, the remaining locations may be examined in any order. access to the external registers of table xxi is accomplished in one of two modes using the cs , ds ( rd ), rw( wr ), and dtack (rdy) inputs. the access modes are intel nonmulti- plexed mode and motorola nonmultiplexed mode. these modes are controlled by the mode input (mode = 0 for inm, mode = 1 for mnm). intel nonmultiplexed mode (inm) mode must be tied low to operate the AD6623 microport in inm mode. the access type is controlled by the user with the chip select ( cs ), read ( rd ), and write ( wr ) inputs. the ready (rdy) signal is produced by the microport to communicate to the user the microport is ready for an access. rdy goes low at the start of the access and is released when the internal cycle is complete. see the timing diagrams for both the read and write modes in the specifications. motorola nonmultiplexed mode (mnm) mode must be tied high to operate the AD6623 microport in mnm mode. the access type is controlled by the user with the chip select ( cs ), data strobe ( ds ), and read/write (rw) inputs. the data acknowledge ( dtack ) signal is produced by the microport to acknowledge the completion of an access to the user. dtack goes low when an internal access is complete and then will return high after ds is deasserted. see the timing diagrams for both the read and write modes in the specifications. the dtack (rdy) pin is configured as an open drain so that multiple devices may be tied together at the microprocessor/ microcontroller without contention. the microport of the AD6623 allows for multiple accesses while cs is held low ( cs can be tied permanently low if the microport is not shared with additional devices). the user can access multiple locations by pulsing the rw( wr ) or ds ( rd ) lines and changing the contents of the external three bit address bus (a[2:0]). external address 7 upper address register (uar) sets the four most significant bits of the internal address, effectively selecting channels 1, 2, 3, or 4 (d2:d0). the autoincrement of read and write are also set (d7:d6). external address 6 lower address register (lar) sets the internal address 8 lsbs (d7:d0). external address 5, softsync this register is write only. bits in this address control the software synchro nization or ?oftsync? of the AD6623 channels. if the user intends to bring up channels with no sy nchronization requirements or op ts fo r ?i n sy n c? c on tro l, then all bits of this regis ter should be written low. two types of sync signals are available with the AD6623. the first is soft sync. soft sync is software syn chroniza- tion enabled through the microport. the second syn chronization method is pin sync. pin sync is enabled by a signal applied to the sync 0-3 pins. see the synchronization section for detailed explanations of the different modes.
rev. a AD6623 ?6 common function registers (not associated with a particular channel) internal address bit ad6622 compatible description AD6623 extensions description 0x000 7 AD6623 extension = 0 1 AD6623 extension = 1 1 6? reserved no change 4r eserved wideband input disable 1 3r eserved dual output enable 1 2r eserved no change 1o ffset binary outputs 1 no change 0c lip wideband i/o 1 no change 0x001 7 first sync only 2 no change 6b eam on pin sync 2 no change 5h op on pin sync 2 no change 4 start on pin sync 2 no change 3c h. d sync0 pin enable 2 no change 2c h. c sync0 pin enable 2 no change 1c h. b sync0 pin enable 2 no change 0c h. a sync0 pin enable 2 no change 0x002 23? unused bist counter 1, 2 0x003 15? unused bist value (read only) channel function registers (0x1xx = ch. a, 0x2xx = ch. b, 0x3xx = ch. c, 0x4xx = ch. d) internal address bit ad6622 compatible description AD6623 extensions description 0x100 17?6 unused ch. a start sync select 2 00: sync0 (see 0x001) 01: sync1 10: sync2 11: sync3 15? ch. a start hold-off counter 2 no change 0x101 7? reserved no change 4c h. a nco amplitude dither enable no change 3c h. a nco phase dither enable no change 2c h. a nco clear phase accumulator on sync no change 1? ch. a nco scale no change 00: ? db no change 01: ?2 db no change 10: ?8 db no change 11: ?4 db no change 0x102 31? ch. a nco frequency value 2 no change 0x103 17?6 unused ch. a hop sync select 2 00: sync0 (see 0x001 hop) 01: sync1 10: sync2 11: sync3 15? ch. a nco frequency update hold?ff counter 2 no change 0x104 15? ch. a nco phase offset 3 no change 3 external address 4 sleep bits in this register determine how the chip is programmed and enables the channels. the program bits (d7:d4) must be set high to allow programming of cmem and dmem for each channel. sleep bits (d3:d0) are used to activate or sleep channels. these can be used manually by the user to bring up a channel by simply writing the required channel high. these bits can also be used in conjunction with the start and sync signals available in external address 5 to synchronize the channels. see the synchronization section for a detailed explanation of different modes. external address 3:0 (data bytes) these registers return or accept the data to be accessed for a read or write to internal addresses. internal counter registers and on-chip ram AD6623 and ad6622 compatibility the AD6623 functions and programmability significantly exceed those of the ad6622 while maintaining ad6622 pin compatibil- ity and functionality when desired. ad6622 compatibility is selected when bit 7 of internal con trol register 0x000 is low. in this state, all AD6623 extended control registers are cleared. while in the ad6622 mode the unused AD6623 pins are three-stated. listed below is the mapping of internal AD6623 registers. ad6622 compatibility is selected by setting 0x000:7 low. in this state, all AD6623 extended control registers are cleared. registers marked as ?eserved?must be written low.
rev. a AD6623 ?7 channel function registers (continued) internal address bit ad6622 compatible description AD6623 extensions description 0x105 17?6 reserved ch. a phase sync select 2 00: sync0 (see 0x001 beam) 01: sync1 10: sync2 11: sync3 15? ch. a nco phase offset update hold?ff counter 2 no change 0x106 7? reserved no change 4? ch. a cic scale, s cic no change 0x107 8? reserved ch. a cic2 decimation, m 2 ? 0x108 11? reserved ch. a cci2 interpolation, l 2 ?, extended 7? ch. a c1c2 interpolation, l 2 ? no change 0x109 7? ch. a c1c5 interpolation, l 5 ? no change 0x10a 15? reserved ch. a rcf tapsb, n rcf ?1 (8 bits) 2 7r eserved ch. a rcf tapsa, n rcf ?1 (new msb) 3 6? ch. a rcf tapsa, n rcf ?1 (7 bits) 2 no change 3 0x10b 7 reserved ch. a rcf coef offset, o rcf (new msb) 3 6? ch. a rcf coefficient offset, o rcf (7 bits) 2 no change 3 0x10c 15?0 unused reserved 9 unused ch. a compact fir input word length 0: 16 bits? i followed by 8 q 1: 24 bits12 i followed by 12 q 8 unused ch. a rcf prbs enable 7c h. a prbs length 2 ch. a rcf prbs length 2 0: 15 0: 15 1: 8,388,607 1: 8,388,607 6c h. a rcf prbs enable ch. a rcf mode select (1 of 3) 3 5c h. a rcf mode select (1 of 2) 2 ch. a rcf mode select (2 of 3) 3 4c h. a rcf mode select (2 of 2) 2 ch. a rcf mode select (3 of 3) 3 00: fir 000: fir 01: fir 001: /4?qpsk 10: qpsk 010: gmsk 11: msk 011: msk 100: fir, compact input resolution 101: 8?sk 110: 3 /8?psk 111: qpsk 3? ch. a rcf (taps per phase) ? 2 no change 3 0x10d 7? ch. a rcf coarse scale (a) no change 3 00: 0 db 01: ? db 10: ?2 db 11: ?8 db 5c h. a rcf phase eq enable no change 4? ch. a serial clock divisor (2, 4, ?4) ch. a serial clock divisor (1, 2,?2) 0x10e 15 ch. a serial fine scale factor enable ch. a unsigned scale factor 3 this is extended to allow values in the range (0?). 14? ch. a rcf unsigned scale factor 3 no change 3 1? reserved reserved 0x10f 17?6 unused ch. a time slot sync select 00: sync0 (see 0x001 beam) 01: sync1 10: sync2 11: sync3 15? ch. a rcf scale hold?ff counter 2 the counter is unchanged, but instead of just scale update, when the counter hits one, the following sequence is initiated: 1. ramp down (if ramp is enabled) 2. update rcf mode select registers marked with ? . 3. ramp up (if ramp is enabled)
rev. a AD6623 ?8 channel function registers (continued) internal address bit ad6622 compatible description AD6623 extensions description 0x110 15? ch. a rcf phase eq coef1 no change 0x111 15? ch. a rcf phase eq coef2 no change 0x112 15? unused ch. a rcf fir?sk magnitude 0 0x113 15? unused ch. a rcf fir?sk magnitude 1 0x114 15? unused ch. a rcf fir?sk magnitude 2 0x115 15? unused ch. a rcf fir?sk magnitude 3 0x116 7? unused ch. a serial data frame input select 0x: internal frame request 10: external sdfi pad 11: previous channel? frame end 5 unused ch. a serial data frame output select 0: serial data frame request 1: serial data frame end 4 unused ch. a serial clock slave (scs) scs = 0: master mode (sclk is an output) scs = 1: slave mode (sclk is an input) 3 unused reserved 2 unused ch. a serial time slot sync enable (ignored in fir mode) 1 unused ch. a ramp interpolation enable 0 unused ch. a ramp enable 0x117 5? unused ch. a mode 0 ramp length, r0? 0x118 4? unused ch. a mode 1 ramp length, r1? 0x119 4? unused ch. a ramp rest time, q (no inputs requested during rest time.) 0x11a?1f unused no change 0x120?3f 15? ch. a data ram no change 0x140?7f 15?4 unused no change 13? unused ch. a ramp ram 0x180?ff 15? ch. a coefficient ram no change this address is mirrored at 0x900?x97f and contiguously extended at 0x980?x9ff notes 1 clear on reset . 2 allows dynamic updates. 3 these bits update after a start or a beam sync. see cr 0x10f (0x000) summation mode control controls features in the summation block of the AD6623. bits 5?: reserved. bit 4: low: wideband input enabled. high: wideband input disabled. bit 3: low: dual output disabled. high: dual output enabled. bit 2: reserved. bit 1: low: output data will be in two? complement. high: output data will be in offset binary. bit 0: low: over-range will wrap. high: over-range will clip to full scale. (0x001) sync mode control bit 7: ignores all but the first sync0 pulse. following this, all 8 bits are cleared to completely mask off subse- quent pulses. bit 6: beam on pin sync0. bit 5: hop on pin sync0. bit 4: high enables the count down of the start hold-off counter. the counter is clocked with the AD6623 clk signal. when it reaches a count of one the sleep bit of the appropriate channel(s) is set low to activate the channel(s). bits 3?: high enables synchronization of these channels. see the synchronization section of the data sheet for detailed explanation. (0x002) bist counter sets the length, in clk cycles, of the built-in self test. (0x003) bist result a read-only register containing the result after a self test. must be compared to a known good result for a given setup to determine pass/fail.
rev. a AD6623 ?9 (27) (0xn00) start update hold-off counter see the synchronization section for detailed explanation. if no synchronization is required, this register should be set to 0. bits 17?6: the start sync select bits are used to set which sync pin will initiate a start sequence. bits 15?: the start update hold-off counter is used to synchronize start?p of AD6623 channels and can be used to synchronize multiple chips. the start update hold-off counter is clocked by the AD6623 clk (master clock). (0xn01) nco control bit 1:0 set the nco scaling per table xxii. table xxii. nco control (0xn01) bit 1 bit 0 nco output level 00 ? db (no attenuation) 01 ?2 db attenuation 10 ?8 db attenuation 11 ?4 db attenuation bit 2: high clears the nco phase accumulator to 0 on either a soft sync or pin sync (see synchronization for details). bit 3: high enables nco phase dither. bit 4: high enables nco amplitude dither. bits 7?: reserved and should be written low. (0xn02) nco frequency this register is a 32-bit unsigned integer that sets the nco frequency. the nco frequency contains a shadow register for synchronization purposes. the nco frequency. can be read back directly; however, the shadow register cannot. nco f clk frequency channel = ? ? ? ? ? ? 2 32 nco output frequency should not exceed approximately 45% of the clk.this makes allowance for the image filtering after d/a conversion. (0xn03) nco frequency update hold-off counter see the synchronization section for detailed explanation. if no synchronization is required, this register should be set to 0. bits 17?6: the hop sync select bits are used to set which sync pin will initiate a hop sequence. bits 15?: the hold-off counter is used to synchronize the change of nco frequencies. (0xn04) nco phase offset this register is a 16-bit unsigned integer that is added to the phase accumulator of the nco. this allows phase synchronization of multiple channels of the AD6623(s). the nco phase offset contains a shadow register for synchronization purposes. the shadow can be read back directly, the nco phase offset cannot. see the synchronization section for details. (0xn05) nco phase offset update hold-off counter see the synchronization section for a detailed explanation. if no synchronization is required, this register should be set to 0. bits 17?6: the phase sync select bits are used to set which sync pin will initiate a phase sync sequence. bits 15?: the hold-off counter is used to synchronize the change of nco phases. (0xn06) cic scale bits 4?: sets the cic scaling per the equation below. cic scale ceil l l cic cic _ = () () log 25 4 2 (28) see the cic section for details. (0xn07) cic2 decimation ?1 (m cic2 ?1) this register is used to set the decimation in the cic2 filter. the value written to this register is the decimation minus one. the cic2 decimation can range from 1 to 512 depending upon the interpolation of the cic2. there is no timing error associated with this decimation. see the cic2 section for further details. (0xn08) cic2 interpolation ?1 (l cic2 ?1) this register is used to set the interpolation in the cic2 filter. the value written to this register is the interpolation minus one. the cic2 interpolation can range from 1 to 4096. l rcic2 must be chosen equal to or larger than m rcic2 and both must be chosen such that a suitable cic2 scalar can be chosen. for more details the cic2 section should be consulted. (0xn09) cic5 interpolation ?1 this register sets the interpolation rate for the cic5 filter stage (unsigned integer). the programmed value is the cic5 interpo- lation ?1. maximum interpolation is limited by the cic scaling available (see the cic section). (0xn0a) number of rcf coefficients ?1 this register sets the number of rcf coefficients and is limited to a maximum of 256. the programmed value is the number of rcf coefficients ?1. there is an a register and a b register at this memory location. value a is used when the rcf is operating in mode 0 and value b is used when in mode 1. the rcf mode bit of interest here is bit 6 of address 0xn0c. (0xn0b) rcf coefficient offset this register sets the offset for rcf coefficients and is normally set to 0. it can be viewed as a pointer which selects the portion of the cmem used when computing the rcf filter. this allows multiple filters to be stored in the coefficient memory space, selecting the appropriate filter by setting the offset. (0xn0c) channel mode control 1 bit 9: high, selecting compact fir mode results in 24-bit serial word length (12 i followed by 12 q). when low, selecting compact fir mode results in 16-bit serial word length (8 i followed by 8 q). bit 8: high enables rcf pseudo-random input select. bit 7: high selects a pseudo-random sequence length of 8,388,607. low selects a pseudo-random sequence length of 15. bits 6?: sets the channel input format as shown in table xxiii. table xxiii. channel inputs bit 6 bit 5 bit 4 input mode 000fir 001 /4-dqpsk 010gsm 011msk 100com pact fir 101 8psk 1103 /8-8psk 111 qpsk
rev. a AD6623 ?0 bit 6 can be set through the serial port (see section on serial word formats). bits 3?: sets (n rcf /l rcf ) ? (0xn0d) channel mode control 2 bits 7?: sets the rcf coarse scale as shown in table xxiv. table xxiv. rcf coarse scale bit 7 bit 6 rcf coarse scale (db) 000 016 10 ?2 11 ?8 bit 5: high enables the rcf phase equalizer. bits 4?: sets the serial clock divider (sdiv) that determines the serial clock frequency based on the following equation. f clk sdiv sclk = + 1 (29) (0xn0e) fine scale factor bits 15?: sets the rcf fine scale factor as an unsigned number representing the values (0,2). this register is shad- owed for synchronization purposes. the shadow can be read back di rectly, the fine scale factor can not. bits 1?: reserved. (0xn0f) rcf time slot sync bits 17?6: the time slot sync select bits are used to set which sync pin will initiate a time slot sync sequence. bits 15?: the fine scale hold-off counter is used to syn- chronize the change of rcf fine scale. see the synchronization section for a detailed explanation. if no synchronization is required, this register should be set to 0. (0xn10?xn11) rcf phase equalizer coefficients see the rcf section for details. (0xn12?xn15) fir-psk magnitudes see the rcf section for details. (0xn16) serial port setup bits 7?: serial data frame start select table xxv. serial port setup bit 7 bit 6 serial data frame start 0x internal frame request 10e xternal sdfi pad 11p revious channel? frame end b it 5: high means sdfo is a frame end, low means sdfo is a frame request. bit 4: high selects serial slave mode. sclk is an input in serial slave mode. bit 3: reserved bit 2: high enables serial time slot syncs (not available in fir mode). bit 1: high enables power ramp coefficient interpolation. bit 0: high enables the power ramp. (0xn17) power ramp length 0 this is the length of the ramp for mode 0, minus one. (0xn18) power ramp length 1 this is the length of the ramp for mode 1, minus one. setting this to zero disables dual ramps. (0xn19) power ramp rest time this is the number of rcf output samples to rest for between a ramp down and a ramp up. (0xn1a?xn1f) unused (0xn20?xn3f) data memory this group of registers contain the rcf filter data. see the rcf section for additional details. (0xn40?xn7f) power ramp coefficient memory this group of registers contain the power ramp coefficients. see the power ramp section for additional details. (0xn80?xnff) coefficient memory this group of registers contain the rcf filter coefficients. see the rcf section for additional details. pseudocode write pseudocode void write_micro(ext_address, int data); main() { /* this code shows the programming of the nco frequency register using the write_micro function defined above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. internal address = 0x102, channel 1 */ /*holding registers for nco byte wide access data*/ int d3, d2, d1, d0; /*nco frequency word (32 bits wide)*/ nco_freq=0x1befefff; /*write chan */ write_micro(7, 0x01); /*write addr */ write_micro(6,0x02); /*write byte 3*/ d3=(nco_freq & 0xff02y 00)>>24; write_micro(3,d3); /*write byte 2*/ d2=(nco_freq & 0xff0000)>>16; write_micro(2,d2); /*write byte 1*/ d1=(nco_freq & 0xff00)>>8; write_micro(1,d1); /*write byte 0, byte 0 is written last and causes an internal write to occur*/ d0=nco_freq & 0xff; write_micro(0,d0); }
rev. a AD6623 ?1 figure 39. AD6623as evaluation board ad9772 a dac 18 bits output data output headers 14 bits to dac 74vcx16500 transceiver external 9v power supply lm317 lm317 lm317 2.5v 3.3v 5v microport i/o header AD6623as tsp four channels serial data in altera flex pld aduc812 microconverter input data headers user parallel data in to pld adm3222 rs-232 line driver serial port of pc 74vcx16500 transceiver input/output headers clk buffers xtal osc. clk frame in/out serial clk in/out dut dac ot iot external clk in microport read pseudocode void read_micro(ext_address); main() { /* this code shows the reading of the nco frequency register using the read_micro function defined above. the variable address is the external address a[2:0] internal address = 0x102, channel 1 */ /*holding registers for nco byte wide access data*/ int d3, d2, d1, d0; /*nco frequency word (32 bits wide)*/ /*write chan */ write_micro(7, 0x01); /*write addr*/ write_micro(6,0x02); /*read byte 0, all data is moved from the internal registers to the interface registers on this access, thus byte 0 must be accessed first for the other bytes to be valid*/ d0=read_micro(0) & 0xff; /*read byte 1*/ d1=read_micro(1) & 0xff; /*read byte 2*/ d2=read_micro(2) & 0xff; /*read byte 0 */ d3=read_micro(3) & 0xff; } AD6623 evaluation pcb and software analog devices offers a fully populated printed circuit board and necessary software to evaluate the AD6623 performance. the software loads the AD6623 program registers, loads rcf (ram coefficient filter) coefficients and programs the onboard fpga and microcontroller. designers should contact their local analog devices product distributor for ordering information. the pcb and software have been designed for maximum flex ibility to accommodate many different applications with minimum need of external devices. please refer to the AD6623 evaluation board manual for detailed information. fir filter design is an extremely important consideration in umts (universal mobile telecommunications system), wideband cdma and other sophisticated data transmission schemes. trans- mitted signals must comply with channel specifications to assure non-interference with neighboring signal channels as well as minimizing inter-symbol interference. the AD6623 fir filter software was designed to fulfill these goals. the latest AD6623 evaluation board and fir filter software are both available from the analog devices web site at http://www.analog.com/ techsupport/designtools/evaluationboards/AD6623.html additional features of the AD6623 pcb kit: ? onboard 14-bit, 175 msps interpolating txdac (ad9772a) for analog reconstruction of digital outputs. (appropriate external anti-alias filter may be required.) ? on board voltage regulation requires only a single 9 v, 1 amp external power supply to power all devices with 2.5 v, 3.3 v and 5 v. ? digital outputs can be cascaded to a second AD6623 pcb for up to 8 output channels from a single dac. ? onboard ?an type?crystal clock or bnc for external single- ended clock oscillator. clk buffers are provided for every driven device ? AD6623 software utilizes the serial port of a personal computer for board programming?upports windows 95, 98, nt and 2000. ? high quality, multi-layer pcb ? comprehensive instruction manual complete with schematics, parts layout diagrams, illustrations.
rev. a AD6623 ?2 applications the AD6623 provides considerable flexibility for the control of the synchronization, relative phasing, and scaling of the individual channel inputs. implementation of a multichannel transmitter invariably begins with an analysis of the output spectrum that must be generated. using the AD6623 to process umts carriers the AD6623 may be used to process two umts carriers, each with an output oversampling rate of 24 (i.e., 92.16 msps). the AD6623 configuration used to accomplish this consists of using two processing channels in parallel to process each umts carrier. please refer to the using the AD6623 to process two umts carriers with 24 oversampling, section. digital to analog converter (dac) selection the selection of a high performance dac depends on a number of factors. the dynamic range of the dac must be considered from a noise and spectral purity perspective. the 14-bit ad9772a is the best choice for overall bandwidth, noise, and spectral purity. in order to minimize the complexity of the analog interpolation filter which must follow the dac, the sample rate of the master clock is generally set to at least three times the maximum analog frequency of interest. in the case where a 15 mhz band of interest is to be up-converted to rf, the lowest frequency might be 5 mhz and the upper band edge at 20 mhz (offset from dc to afford the best image reject filter after the first digital if). the minimum sample rate would be set to 65 msps. consideration must also be given to data rate of the incoming data stream, interpolation factors, and the clock rate of the dsp. multiple tsp operation each of the four transmit signal processors (tsps) of the AD6623 can adequately reject the interpolation images of narrow band- width carriers such as amps, is-136, gsm, edge, and phs. wider bandwidth carriers such as is-95 and imt2000 require a coordinated effort of multiple processing channels. this section demonstrates how to coordinate multiple tsps to create wider bandwidth channels without sacrificing image rejection. as an example, a umts carrier is modulated using four tsp channels (an entire AD6623). the same principles can be applied to different designs using more or fewer tsps. this section does not explore techniques for using multiple tsps to solve problems other than serial port or rcf throughput. designing filter coefficients and control settings for de-interleaved tsps is no harder than designing a filter for a single tsp. for example, if four tsps are to be used, simply divide the input data rate by four and generate the filter as normal. for any design, a better filter can always be realized by incrementing the number of tsps to be used. when it is time to program the tsps, only two small differences must be programmed. first, each channel is configured with exactly the same filter, scalers, modes and nco frequency. since each channel receives data at one-quarter the data rate and in a staggered fashion, the start hold-off counters must also be staggered (see ?rogramming multiple tsps?section). second, the phase offset of each nco must be set to match the demultiplexed ratio (in this example). thus the phase offset should be set to 90 degrees (16384 which is one-quarter of a 16-bit register). determining the number of tsps to use there are three limitations of a single tsp that can be overcome by deinterleaving an input stream into multiple tsps: serial port bandwidth, the time restriction to the rcf impulse response length (nrcf), and the dmem restriction to nrcf. if the input sample rate is faster than the serial port can accept data, the data can be de-interleaved into multiple serial ports. recalling from the serial port description, the sclk frequency (f sclk ) is determined by the equation below. to minimize the number of processing channels, sclkdivider should be set as low as possible to get the highest f sclk- that the serial data source can accept. f f sclkdivider sclk clk = + 1 (30) a minimum of 32 sclk cycles are required to accept an input sample, so the minimum number of tsps (ntsp) due to limited serial port bandwidth is a function of the input sample rate (f in ), as shown in the equation below. n ceil f f tsp in sclk ? ? ? ? ? ? 32 (31) for example for a umts system, we will assume f clk = 76.8 mhz, and the serial data source can drive data at 38.4 mbps (sclkdivider = 0). to achieve f in = 3.84 mhz, the minimum n tsp is 3 with a serial clock f sclk = 52 mhz which is a limitation of the serial port (this is tsp channels, not tsp ics). multiple tsps are also required if the rcf does not have enough time or dmem space to calculate the required rcf filter. recalling the maximum n taps ?equation from the rcf description, are three restrictions to the rcf impulse response length, n rcf . time restriction cmem restriction nl rcf rcf ? ? ? ? ? ? ? min 1 2 ,16 256 (32) dmem restriction where: ll l l m nf f rcf cic cic cic tsp clk in = = 5 2 2 (33) de-interleaving the input data into multiple tsps extends the time restriction and may possibly extend the dmem restriction, but will not extend the cmem restriction. de-interleaving the input stream to multiple tsps divides the input sample rate to each tsp by the number of tsps used (n tsp ). to keep the output rate fixed, l must be increased by a factor of n ch , which extends the time restriction. this increase in l may be achieved by increasing any one or more of l rcf , l cic5 , or l cic2 within their normal lim its. achieving a larger l by increasing l rcf instead of l cic5 or l cic2 will relieves the dmem restriction as well. in a umts example, n tsp = 4, f clk = 76.8 mhz, and f in = 3.84 mhz, resulting in l = 80. factoring l into l rcf = 10, l cic = 8, and l cic2 = 1 results in a maximum n rcf = 40 due to the time restriction. figure 42 shows an example rcf impulse response which has a frequency response as shown in figure 43
rev. a AD6623 ?3 from 0 hz to 7.68 mhz (f in l rcf /n tsp ). the composite rcf and cic frequency response is shown in figure 44, on the same frequency scale. this figure demonstrates a good approximation to a root-raised-cosine with a roll-off factor of 0.22, a passband ripple of 0.1 db, and a stopband ripple better than ?0 db until the lobe of the first image which peaks at ?0 db about 7.68 mhz from the carrier center. this lobe could be reduced by shifting more of the interpolation towards the rcf, but that would sacrifice near in performance. as shown, the first image can be easily rejected by an analog filter further up the signal path. scaling must be considered as normal with an interpolation factor of l, to guarantee no overflow in the rcf, cic, or ncos. the output level at the summation port should be calculated using an interpolation factor of l/n tsp . programming multiple tsps configuring the tsps for de-interleaved operation is straight forward. all the channel registers and the cmem of each tsp are programmed identically, except the start hold-off counters and nco phase offset. in order to separate the input timing to each tsp, the hold-off counters must be used to start each tsp successively in response to a common start sync. the start sync may originate from the sync pin or the microport. each subsequent tsp must have a hold-off counter value l/n tsp larger than its predecessor?. if the tsps are located on cascaded AD6623s, the hold-off counters of the upstream device should be incremented by an additional one. in the umts example, l = 80 and n tsp = 4, so to respond as quickly as possible to a start sync, the hold-off counter values should be 1, 21, 41, and 61. driving multiple tsp serial ports when configured properly, the AD6623 will drive each sdfo out of phase. each new piece of data should be driven only into the tsp that pulses its sdfo pin at that time. in the umts example in figure 41, l = 80 and n tsp = 4, so each serial port need only accept every fourth input sample. each serial port is shifting at peak capacity, so sample 1, 2, and 3 begin shifting into serial ports b, c, and d before sample 0 is com- pleted into serial port a. sdfoa sdfob sdfoc sdfod 04 15 2 7 6 3 figure 41. umts example coefficient 1.0 0.5 05 magnitude 10 0.0 15 20 25 30 35 40 figure 42. typical impulse response for wbcdma (wide-band code division multiple access) ram coef filter cic nco summation block cic nco cic nco cic nco data re-formatter dac ram coef filter ram coef filter ram coef filter 76.8 msamples/sec 76.8msps 76.8msps 76.8msps 76.8msps 9.6msps 9.6msps 9.6msps 9.6msps 0.96 mcps 0.96 mcps 0.96 mcps 0.96 mcps 3.84 mcps 32 32 32 32 32 i q i q i q i q complex signal 32 bits (16, i, 16 q) real or imaginary signal figure 40. driving multiple tsp serial ports
9/16/02 12:30 pm_tg rev. a AD6623 ?4 khz 0 1000 dbc 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 2000 3000 4000 5000 6000 7000 8000 9000 10000 figure 43. ram coefficient filter, frequency response for wbcdma khz 0 1000 dbc 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 2000 3000 4000 5000 6000 7000 8000 9000 10000 cic rolloff composite AD6623 response ideal filter figure 44. rcf and cic, frequency response for wbcdma using the AD6623 to process two umts carriers with 24 output rate overview the AD6623 may be used to process two umts carriers, each with an output rate of 24 (i.e., 92.16 msps). the AD6623 configuration used to accomplish this consists of using two pro- cessing channels in parallel to process each umts carrier. the ideology behind the parallel processing approach is that each channel operates on half of the input samples, processing every other sample. the reason is that the serial input data rate is limited to 3.25 msps for 16-bit i and 16-bit q data (104 msps/32). the first channel of each pair begins processing the first input sample immediately. the second channel begins processing after a specific delay so that the two channels essentially will be operating 180 degrees out of phase with each other. since each channel processes only half the input samples and thus receives input data at half the original rate, each channel has twice the original amount of time available for processing. this in turn makes available twice the original number of taps, resulting in much improved digital filtering capability. to maximize the number of available fir filter taps, the highest possible input rate should be used. therefore, this application note assumes an input sample rate of 3.84 msps and an output data rate of 24 (i.e., 92.16 msps), which in conjunction with the 1 input rate (assumes two channels used per carrier at 1.92 msps) results in a total decimation value of 24. since two AD6623 channels will be used for each carrier, each channel will operate with a total interpolation of forty-eight, resulting in a total of 24 taps for the fir filter. all channels must be configured with the same fir filter coefficients, decimation and interpolation values, and scaling values. configuring the AD6623 the serial input data ports need run at 1.92 msps by using f sclk = 92.16 msps, with sclk divider = 0 (0x0d, bits 4- 0 = 0). in order to properly process a umts channel across two channels the channels need to be synchronized. the channel starts will be delayed by precise input clock periods, and the nco? will be independently phased to account for starting channels out of phase. the final output summation stage adds data from separate channels together. it should be noted that all serial output ports must be configured for serial bus master mode, since sclks cannot be run at 92.16 mhz in slave mode. when initiating carrier processing, care should be taken to ensure that both the primary and secondary processing channels are started with precise relative timing (preferably by a pulse on one of the sync pins). the device is configured with the following filtering parameters: l rcf = 6 n taps = 24 l cic5 = 8 l cic2 = 1 m cic2 = 1 sclk = 92.16 AD6623 register configuration to process two umts carriers with 24 output rate, the AD6623 must be properly configured. the following sections describe the required register settings for this configuration. interpolation, decimation, and scaling values specified for the following regis- ters were used to obtain the reference filter response shown in the performance section of this data sheet. other registers may be set as needed for any individual application. for registers with bit fields, the following symbols are used: 0, 1: bit must be set to zero or one as indicated. ?? bit is dependent on the user? application, but must be the same for both channels of a processing pair. ? ? bit can be set at user? discretion, regardless of the channel used. coefficient memory (0x900?x9ff, bits 15:0) each pair of processing channels must be assigned the same fi r filter coefficients. twenty-four taps must be used, typically loaded into addresses 0x900-0x9ff.
rev. a AD6623 ?5 the fir filter coefficients for the reference filter are: ?81 ?01 24803 2420 ?16 ?461 14446 1729 ?084 ?366 1588 ?09 ?09 1588 ?366 ?084 1729 14446 ?461 ?16 2420 24803 ?01 ?81 start sync control register (0xn00, bits 17:16) the settings in this register must be the same for each pair of processing channels. start holdoff counter (0xn00, bits 15:0) the secondary channel of each processing pair needs to be configured such that it begins processing 180 degrees out of phase with the primary channel. the start holdoff counter (shc) of the secondary channel is set to the value of the primary channel plus ltot/2, where ltot is the overall channel interpolation. scc scc l ndchannel stchannel tot 21 2 =+ (34) for example, in the case of ltot = 48, the primary channel of each processing is set to two, while the secondary channel? start holdoff counter is set to twenty-six. nco frequency registers (0xn02, bits 31:0) each pair of processing channels must be assigned the same nco frequency register values. nco frequency holdoff counter (0xn03, bits 15:0) each pair of processing channels must be assigned the same nco holdoff counter value. nco phase offset register (0xn04, bits 15:0) the nco of the secondary channel must have its initial phase set such that, when it begins processing, its phase is equal to that of the primary channel? phase. the equation is given by: ncophaseoffset round frac lf f tot nco samp =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 16 (35) where round () returns the nearest integer of its argument, frac () returns the fractional part of its argument, f nco is the desired nco frequency, and f samp is the desire output sample rate. nco phase offset update holdoff (0xn05, bits 15:0) each pair of processing channels must be assigned the same nco phase offset update holdoff value. cic scale (0xn06, bits 4:0) each pair of processing channels must use a value of seventeen for this register (s cic = 12). rcic2 decimation-1 (0xn07, bits 8:0) each pair of processing channels must use a value of zero for this register (rcic2 decimation = 0). rcic2 interpolation-1 (0xn08, bits 7:0) each pair of processing channels must use a value of zero for this register (rcic2 interpolation = 0). cic5 interpolation-1 (0xn09, bits 7:0) each pair of processing channels must use a value of seven for this register (cic5 interpolation = 7). rcf number of taps-1 (0xna0, bits 7:0) each pair of processing channels must use a value of twenty- three for this register (nrcf-1 = 23). rcf coefficient offset (0xn0b, bits 7:0) each processing channel must specify the offset of the address where its coefficients begin (typically zero). rcf mode (0xn0c, bits 9:4) each pair of processing channels must set all these bits to zero. rcf mode (0xn0c, bits 3:0) each pair of processing channels must be assigned the same number of taps per phase which in this case is four. serial data frame input select (0xn16, bits 7:6) the secondary channel of each processing pair needs to be configured such that it begins processing data after the primary channel? frame end. this is done by setting the serial data frame input select bits high (bits 7:6 = 11). serial data frame output select (0xn16, bits 5) the primary channel of each processing pair needs to be configu red such that it is configured for serial data frame request (bit 5 = 0). serial clock slave (0xn16, bits 4) each pair of processing channels must be configured in master mode (bit 4 = 0). performance the filter performance of the AD6623? dual-channel processing approach is shown in figure 45. this filter uses 24 taps, with rcf interpolation of 6, cic5 interpolation of 8, and rcic2 interpolation and decimation of 1 and 1, respectively. the near rejection at 5 mhz is 65 dbc, and rejection at 10 mhz is 80 dbc, with a passband ripple of 0.25 db. the register settings implement- ing this filter are outlined in the AD6623 register configuration section of this technical note.
rev. a AD6623 ?6 mhz ?0 dbc 10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ? ? ? ? 0 2 4 6 8 10 cic response composite r esponse d esired r esponse figure 45. composite response to first cic5 null thermal management the power dissipation of the AD6623 is primarily determined by three factors: the clock rate, the number of channels active, and the distribution of interpolation rates. the faster the clock rate the more power dissipated by the cmos structures of the AD6623 and the more channels active the higher the overall power of the chip. low interpolation rates in the cic stages (cic5, cic2) results in higher power dissipation. all these factors should be analyzed as each application has different thermal requirements. the AD6623 128-lead mqfp is specially designed to provide excellent thermal performance. to achieve the best performance the power and ground leads should be connected directly to planes on the pc board. this provides the best thermal transfer from the AD6623 to the pc board.
rev. a AD6623 ?7 outline dimensions 128-lead plastic quad flatpack [mqfp] (s-128a) dimensions shown in millimeters top view (pins down) 1 38 39 65 64 102 128 103 0.27 0.17 0.50 bsc 1.03 0.88 0.73 seating plane 3.40 max coplanarity 0.10 max 0.50 0.25 2.90 2.70 2.50 17.45 17.20 16.95 14.20 14.00 13.80 20.20 20.00 19.80 23.45 23.20 22.95 196-lead chip scale ball grid array [cspbga] (bc-196) dimensions shown in millimeters detail a 1.70 max seating plane 0.30 min detail a 0.70 0.60 0.50 ball diameter 0.20 coplanarity 13.00 bsc sq a b c d e f g h j k l m n p 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 1.00 bsc ball pitch 15.00 bsc sq top view bottom view a1 corner compliant to jedec standards mo-192aae-1 notes 1. actual position of the ball grid is within 0.20 of its ideal position relative to the package edges. 2. actual position of each ball is within 0.10 of its ideal position relative to the ball grid. 3. center dimensions are nominal. ball a1 indicator
?8 c02768??/02(a) printed in u.s.a. rev. a revision history location page 9/02?ata sheet changed from rev. 0 to rev. a. changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 added control register address notation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 added serial data framing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 edits to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 added notes and legend to figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 changes to interpolating fir filter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 renamed and changed table v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 changes to /4-dqpsk modulation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to 8-psk modulation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to 3 /8-8-psk modulation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to msk look-up table section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to gmsk look-up table section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to qpsk look-up table section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to phase equalizer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 replaced table xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 replaced scale and ramp section with fine scale and power ramp section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 new fine scaling section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 new rcf power ramping section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 inserted new figures 26-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 removed rcic2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 changes to figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 replaced table xii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 changes to table xiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 inserted new the rcic2 resampling interpolation filter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 replaced equation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 added frequency response of rcic2 heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 added programming guidelines for AD6623 cic filters heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 changes to table xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 changes to numerically controlled oscillator/tuner section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 added dual 18-bit output configuration heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 added output data format heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 added text to output data format section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 added output clip detection heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 added cascading multiple AD6623s heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 added selection of real and complex output data types heading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 added hold-off counters and shadow registers section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 changes to start with pin sync section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 changes to hop with pin sync section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 changes to beam with pin sync section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 added time slot (ramp) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 added new figure 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 added new figure 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 removed channel function registers section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 changes to table xxi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 changes to external address 5, software sync section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 changes to AD6623 and ad6622 compatibility section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 changes to common function registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 changes to channel function registers table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 changes to (0x001) sync mode control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 changes to (0xn02) nco frequency section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 changes to (0xno0f) rcf time slot sync section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 changes to (0xn16) serial port setup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 edits to table xxiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 changes to (0xn40?xn7f) power ramp coefficient memory section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 changes to (0xn80?xnff) coefficient memory section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 added new AD6623 evaluation pcb and software section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 added new figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 added using the AD6623 to process two umts carriers with 24 output rate section . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AD6623

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